JPH01124706U - - Google Patents
Info
- Publication number
- JPH01124706U JPH01124706U JP2083488U JP2083488U JPH01124706U JP H01124706 U JPH01124706 U JP H01124706U JP 2083488 U JP2083488 U JP 2083488U JP 2083488 U JP2083488 U JP 2083488U JP H01124706 U JPH01124706 U JP H01124706U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- phase
- limiter
- constant current
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 10
- 230000010363 phase shift Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第1図は、本考案のクオドラチユア検波回路の
一実施例を示す回路図、第2図は、本考案のクオ
ドラチユア検波回路の他の実施例を示す回路図、
第3図は、本考案のクオドラチユア検波回路の他
の実施例を示す回路図、第4図は、従来のクオド
ラチユア検波回路の例を示す図である。
1:アンテナ、2:フロントエンド、3:リミ
ツタ回路、4:移相回路、5:掛算回路、6,6
′:差動増幅器、7:クオドラチユア検波回路、
8,9:電流ミラー回路、10,11:出力端子
、12:接地端子、13:電源端子、14:レベ
ルシフト回路。
FIG. 1 is a circuit diagram showing one embodiment of the quadrature detection circuit of the present invention, and FIG. 2 is a circuit diagram showing another embodiment of the quadrature detection circuit of the present invention.
FIG. 3 is a circuit diagram showing another embodiment of the quadrature detection circuit of the present invention, and FIG. 4 is a diagram showing an example of a conventional quadrature detection circuit. 1: Antenna, 2: Front end, 3: Limiter circuit, 4: Phase shift circuit, 5: Multiplier circuit, 6, 6
': Differential amplifier, 7: Quadrature detection circuit,
8, 9: current mirror circuit, 10, 11: output terminal, 12: ground terminal, 13: power supply terminal, 14: level shift circuit.
Claims (1)
と、該リミツタ出力の正相と反転相からなる定電
流化されたリミツタ出力を導出する第1の差動増
幅器と、該移相回路により90°位相シフトされ
たリミツタ出力と該第1の差動増幅器からの正相
と反転相からなる定電流化されてリミツタ出力が
入力される第2と第3の差動増幅器からなる掛算
回路から構成されたことを特徴とするクオドラチ
ユア検波回路。 (2) リミツタ出力を位相シフトさせる移相回路
と、定電流源回路に接続されたトランジスタ差動
対と該差動対トランジスタのコレクタに夫々接続
される第1と第2の負荷回路からなる第1の差動
増幅回路と、該移相回路により90°位相シフト
されたリミツタ信号と該第1の差動増幅器から正
相と反転相からなる定電流化されたリミツタ出力
とが入力される第2と第3の差動増幅器からなる
掛算回路とで構成されたクオドラチユア検波回路
であつて、該第1と該第2の負荷回路が該第2と
該第3の差動増幅器の夫々の差動対に接続された
トランジスタと共に第1と第2の電流ミラー回路
を形成することによつて、リミツタ回路と該掛算
回路が結合されたことを特徴とするクオドラチユ
ア検波回路。 (3) 正相と反転相のリミツタ出力が夫々供給さ
れる第1と第2のトランジスタと、それらのトラ
ンジスタのエミツタに接続された電流源回路から
なる第1と第2のレベルシフト回路をクオドラチ
ユア検波回路の前段に具え、該第1と該第2のレ
ベルシフト回路から得られるリミツタ出力が供給
され定電流化されたリミツタ出力を導出する第1
の差動増幅器と、該レベルシフト回路を介して得
られるリミツタ出力を位相シフトさせる移相回路
と、該移相回路から90°位相シフトされたリミ
ツタ出力と該第1の差動増幅器から正相と反転相
からなる定電流化されたリミツタ出力が入力され
る第2と第3の差動増幅器からなる掛算回路から
構成されたことを特徴とするクオドラチユア検波
回路。 (4) 前記第1の差動増幅回路が、定電流源回路
と、エミツタが共通接続されて該定電流源回路に
接続された第1乃至第4のトランジスタと、該第
1と第3のトランジスタの夫々のコレクタに接続
された第1と第3のダイオードからなり、該第3
のダイオードが第5のトランジスタと共に電流ミ
ラー回路を形成し、該電流ミラー回路の出力段の
トランジスタが移相回路に接続されてなる請求項
第1項と第2項及び第3項記載のクオドラチユア
検波回路。[Claims for Utility Model Registration] (1) A phase shifting circuit that shifts the phase of a limiter output, and a first differential amplifier that derives a constant current limiter output consisting of a positive phase and an inverted phase of the limiter output. , a limiter output whose phase has been shifted by 90 degrees by the phase shift circuit, and a second and third differential amplifier, into which the constant current limiter output consisting of the positive phase and inverted phase from the first differential amplifier is input. A quadrature detection circuit comprising a multiplication circuit consisting of an amplifier. (2) A phase shifting circuit that shifts the phase of the limiter output, a differential pair of transistors connected to a constant current source circuit, and a first and second load circuit connected to the collectors of the differential pair transistors, respectively. 1 differential amplifier circuit, a limiter signal whose phase is shifted by 90 degrees by the phase shift circuit, and a constant current limiter output consisting of a positive phase and an inverted phase from the first differential amplifier. 2 and a multiplication circuit consisting of a third differential amplifier, wherein the first and second load circuits calculate the difference between the second and third differential amplifiers. A quadrature detection circuit characterized in that a limiter circuit and the multiplication circuit are combined by forming first and second current mirror circuits together with transistors connected in a dynamic pair. (3) The first and second level shift circuits, which consist of first and second transistors to which positive-phase and inverted-phase limiter outputs are supplied, respectively, and a current source circuit connected to the emitters of these transistors, are configured as a quadrature. A first circuit provided before the detection circuit and configured to receive the limiter outputs obtained from the first and second level shift circuits and derive a constant current limiter output.
a differential amplifier, a phase shift circuit that shifts the phase of the limiter output obtained through the level shift circuit, and a limiter output whose phase is shifted by 90 degrees from the phase shift circuit and a positive phase output from the first differential amplifier. 1. A quadrature detection circuit comprising a multiplication circuit comprising second and third differential amplifiers to which a constant current limiter output having an inverted phase and a constant current are input. (4) The first differential amplifier circuit includes a constant current source circuit, first to fourth transistors whose emitters are commonly connected and connected to the constant current source circuit, and the first and third transistors. a first and a third diode connected to respective collectors of the transistor;
The quadrature detection according to claims 1, 2 and 3, wherein the diode forms a current mirror circuit together with a fifth transistor, and the output stage transistor of the current mirror circuit is connected to a phase shift circuit. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2083488U JPH01124706U (en) | 1988-02-19 | 1988-02-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2083488U JPH01124706U (en) | 1988-02-19 | 1988-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01124706U true JPH01124706U (en) | 1989-08-24 |
Family
ID=31237538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2083488U Pending JPH01124706U (en) | 1988-02-19 | 1988-02-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01124706U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61140206A (en) * | 1984-12-13 | 1986-06-27 | Matsushita Electric Ind Co Ltd | Quadrature detection circuit |
-
1988
- 1988-02-19 JP JP2083488U patent/JPH01124706U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61140206A (en) * | 1984-12-13 | 1986-06-27 | Matsushita Electric Ind Co Ltd | Quadrature detection circuit |
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