JPH01126630U

JPH01126630U -

Info

Publication number: JPH01126630U
Application number: JP1656988U
Authority: JP
Priority date: 1988-02-10
Filing date: 1988-02-10
Publication date: 1989-08-30

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例によるレベル変換回
路を示す回路図、第２図は従来のレベル変換回路
の一例を示す回路図である。１……入力端子、２……出力端子、３……第２
の電源端子、４……第１の電源端子、５……第１
のＦＥＴ、６……第５のＦＥＴ、７……第３のＦ
ＥＴ、８……第４のＦＥＴ、９……第２のＦＥＴ
、１０……第６のＦＥＴ。 FIG. 1 is a circuit diagram showing a level conversion circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional level conversion circuit. 1...Input terminal, 2...Output terminal, 3...Second
power supply terminal, 4...first power supply terminal, 5...first power supply terminal
FET, 6...5th FET, 7...3rd FET
ET, 8...Fourth FET, 9...Second FET
, 10...6th FET.

Claims

[Scope of utility model registration request]

A third field effect transistor whose source is connected to the input terminal of the first field effect transistor whose gate is common, and whose drain is connected to the gate of the second field effect transistor whose drain is common and the source of the first field effect transistor whose source is common to the first power supply terminal. and the drain of the fourth field effect transistor, and the gate of a fifth field effect transistor whose source is grounded to the second power supply terminal is connected to the input terminal,
Its drain is connected to the drain of the third field effect transistor, the gate of the fourth field effect transistor, and the gate of a sixth field effect transistor whose source is grounded to the first power supply terminal, and A level conversion circuit characterized in that a source of a sixth field effect transistor and a drain of a sixth field effect transistor are connected to an output terminal.