JPH01128456A - Surface packaging type semiconductor device and leadframe - Google Patents

Abstract

PURPOSE:To assure satisfactory soldering over the whole surface between corners of both edges of a lead with respect to a lead surface subject to coining by forming a stepped surface on the lead surface by subjecting part of a lead frame where a sag thereof is produced by a press and providing the corners on the edges of the lead frame, each corner having a substantially right angle. CONSTITUTION:In a microminiature transistor 8, a lead 1 has a structure where any sag produced upon manufacture has been corrected. That is, any sag on the edge of the lead 1 is subject to coining and jence is eliminated, and instead a flat surface 14 lowered by one step is provided. The flat surface 14 is formed on the part of the sag 2 by coining by a pair of presses composed of top and bottom forces. Accordingly, the lead 1 is comprised of a wide flat surface 15 and the flat surface 14 lowered by one step and extending to both sides of the wide flat surface 15. Upon dipping a solder in the protuberant lead 1, the solder 3 is sticked in a protuberant state at the center thereof to the lead over a region from the corner 16 of the flat surface 14 through the wide flat surface 15 to the corner 16 of the other flat surface 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a surface mount type semiconductor device, particularly a surface mount type semiconductor device whose leads have good solder wettability, and a lead frame used for assembling the same.

[Conventional technology]

Electronic devices are required to be more densely packaged from a functional standpoint, and to be lighter, smaller, and thinner from a packaging standpoint.

For this reason, a large number of electronic components are incorporated into electronic devices (
There is a shift towards structures that allow surface mounting.

Furthermore, in order to reduce the manufacturing cost of electronic components, resin packages are often used as the package form because they are made of cheap materials and have good productivity.

An ultra-small transistor is known as one such semiconductor device. For examples of ultra-small transistors, see, for example, the Industrial Research Council [Electronic Materials J.
March 1972 issue, published March 1, 1972, P91-
It is described on page 96.

On the other hand, for the purpose of reducing manufacturing costs of electronic devices, efforts are being made to automate the mounting of electronic components.

In addition, one method for fixing electronic components such as the aforementioned ultra-small transistors is to temporarily attach the electronic components onto a wiring board printed with solder paste (the surface tension of the solder paste causes the leads to come into contact with the solder paste). ), methods of reflowing solder are known.

An example of a document that describes automatic mounting technology in detail is "Electronic Materials J, March 1979 issue, March 1, 1979, published by Kogyo Kenkyukai, pages 54 to 5B.

By the way, the package size of the ultra-small transistor is very small, around 1 to 2 mm in length, width, and height, and it also has two leads protruding from one side of the package and one from the other side. Since the product width is less than 3 mm even if it is included, and the width of the protruding leads is also narrow, the mounting area for attaching the ultra-small transistor to the wiring board must be small.

Therefore, it is desired that ultra-small transistors be more securely fixed by soldering.

On the other hand, an example of improving the suction of solder when mounting a microtransistor is described in Japanese Patent Laid-Open No. 61-64146. This document discloses a technique in which the cross section of the lead of a hybrid compatible element is made into a substantially trapezoidal shape to make the lead thinner, thereby improving the suction of solder.

Furthermore, the microtransistor is assembled using a lead frame. The lead frame is formed by forming a thin metal plate by pressing (punching) or etching. Lead frames are described in "Electronic Materials J, August 19B2, August 1, 1980, published by Kogyo Kenkyukai, pages 69 to 74.

This document describes trends in press working of lead frames, such as the occurrence of warpage due to punching of ultra-thin plates.

[Problem that the invention seeks to solve]

Lead frames formed by punching as described above have problems with solder dip.

That is, when the leads protruding from the periphery of the package 7 are soldered-dipped, as shown in FIG. 20, if there is a droop (curved surface) 2 on both edges of the upper surface of the lead 1 due to punching when forming the lead frame, this A phenomenon occurs in which the solder 3 adheres only thinly to the droop 2, for example, the areas indicated by a and b. Further, due to punching during formation of the lead frame, a protruding burr 4 is generated on the surface on the back side of the surface where the droop 2 is formed.

However, even if this portion of solder 4 is thin, the entire portion is covered with solder 3.

Incidentally, in the final manufacturing process of a semiconductor device, a product name and the like are stamped on the surface of the package.

In this stamp, the stamped ink is, for example, 1
It is baked at 50"C for 1 to 2 hours. Therefore, due to the heat during baking, the a and bS of the lead I
Solder in the Jf range is thin and has a wide range, so p
b-rich, the composition changes, and oxidation occurs.For this reason, when a finished semiconductor device is surface-mounted on a wiring board, as shown in FIGS. 18 and 19, the wiring board 5 When a solder cream (not shown) is provided on the wiring layer 6 of the wiring layer 6 and the leads 1 are placed on this solder cream and mounted by reflowing, the solder cream may be Even if it melts, solder 3
As clearly shown in FIG. 19, the solder 3 is not attracted to the upper surface of the lead 1, making it impossible to perform reliable soldering in which the solder 3 covers the entire circumference of the lead 1. This type of soldering is not only problematic in terms of reliability, but also in terms of yield as it is often determined to be poor in appearance during inspection.

In addition, this kind of suction of solder 3 onto lead 1 is as follows:
It is not necessarily sufficient to simply form the upper edge of the lead l into a flat inclined surface as in the above-mentioned known example.

That is, during solder dipping, the solder on the sloped surface portion is attracted to the wide upper surface above it, and there is not enough solder left on the sloped surface to fix the leads.

An object of the present invention is to provide a surface-mounted semiconductor device with good solder mountability.

Another object of the present invention is to provide a surface-mounted semiconductor device with high mounting yield and high mounting confidence.

Another object of the present invention is to provide a lead frame with good solder mounting properties.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in the present invention, a lead frame formed by a press is used when assembling a surface-mounted semiconductor device, and after this lead frame is patterned by a press, the portions formed by the press are removed. It is coined to form a stepped surface, and the edge is provided with a corner portion having an angle close to a right angle. As a result, when a solder dip is applied to such a lead, solder is sufficiently adhered to the coined lead surface over the entire surface between the corners of both edges of the lead. Therefore, in a semiconductor device manufactured using such a lead frame, the leads protruding from the package have sufficient solder around the entire circumference.

[Effect]

According to the above-mentioned means, in the semiconductor device of the present invention, the droop portion of the lead is corrected by coining, and the solder is adhered to the entire surface between the corner portions of both edges caused by the correction. For this reason, the solder adheres to the entire circumference of the leads, so when a semiconductor device is mounted on a wiring board, the solder adhered to the leads and the solder cream provided on the bottom side of the leads are damaged by heat. Melt and become one. Since the surface of the lead frame is not oxidized, the integrated solder is easily absorbed to the top surface of the leads. As a result, the entire circumference of the lead is covered with solder, so that secure and reliable solder fixation can be performed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view showing a part of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged sectional view of a lead, FIG. 3 is a perspective view of the semiconductor device in an inverted state, and FIG.
FIG. 5 is a flowchart showing a method of manufacturing a semiconductor device, and FIGS. 6 to 16 are diagrams showing a state of manufacturing a semiconductor device of the present invention. Fig. 6 is a plan view showing the lead frame, Fig. 7 is a sectional view showing the leads of the lead frame, Fig. 8 is an enlarged sectional view showing the state in which the coining process is applied to the droop of the lead, and Fig. 9 is a sectional view showing the coining process. FIG. 10 is a plan view showing a plated lead frame, FIG. 11 is a sectional view showing a chip bonding state, FIG. 12 is a sectional view showing a wire bonding state, and FIG. 13 is a sectional view showing a lead frame. 14 is a plan view showing the lead frame in the molded state, FIG. 15 is a sectional view showing the mounted semiconductor device, and FIG. 16 is a part of the solder-fixed state. It is an enlarged sectional view.

In this embodiment, an example in which the present invention is applied to an ultra-small transistor (semiconductor device) whose package size is several mm will be described. The ultra-small transistor has a structure as shown in FIG. For convenience of explanation, FIG. 3 shows a microtransistor in an inverted state.

The ultra-small transistors 8 are one on one side of the resin (for example, epoxy resin) package 7, two on the other side,
It has a structure in which part 1 of a total of three glues protrudes. This figure shows a state in which the ultra-small transistor 8 is turned over so that its mounting surface faces upward. The package 7 has, for example, a length of 1.5 mm and a width of 2.5 mm. 8mm and height 1.1mm. Further, the lead 1 is bent toward the mounting surface near the root of the package 7, and its tip portion is bent outward again to form a fixing portion 9 at the tip. The lead 1 has a width of 0°4 mm, a thickness of 0.16 mm, and a protruding length from the side of the package 7 of 0.
．． It is 5mm. This fixing portion 9 is flush with the mounting surface, and is connected to a conductive layer of a wiring board or the like by solder or the like during mounting.

On the other hand, the inner ends of the leads 1 extending inside the package 7 are each wide, and the central glue lead l has a tab 10.
The leads 1 on both sides constitute wire connection parts 11, respectively. This is to obtain an area for chip bonding and wire bonding, but also serves to prevent the stepped portion beam 1 from coming off from the pan cage 7.

Although not shown in the figure, a plating film made of a silver layer is provided on the tab 10 and the wire connection portion 11 of the lead l, respectively, and on the plating film of the tab 10, a semiconductor element ( A chip (chip) 12 is fixed, and a wire 13 is connected to the plating film of the wire connection portion 11. The wire 13 is configured to electrically connect an electrode (not shown) of the chip 12 and the inner end of the lead 1, that is, the wire connection portion 11.

Moreover, in this ultra-small transistor 8, the lead l
The structure has been corrected for any damage that occurred during its manufacture. That is, the sagging portion of the edge of the lead 1 is coined to eliminate the sag, and in its place is provided with a lower flat surface 14, as shown in FIGS. 1 and 2. This lower flat surface 14 is shown in FIGS.
As shown in the figure, a pair of presses consisting of a lower mold 17 and an upper mold 18 are crushed and coined, and the drop 2 is
Formed in the area. Therefore, the lead 1 is composed of a wide flat surface 15 and a lower flat surface 14 extending on both sides of the wide flat surface 15.

The lower flat surface 14 is, for example, 0.01 mm lower than the wide flat surface 15 and has a length of 0.05 mm to 0.1 mm.
mm. Furthermore, the edge of the lower flat surface 14 has a substantially right-angled corner 16. Furthermore, the stepped portion between the wide flat surface 15 and the lower flat surface 14 is also at right angles.

As a result, when the lead 1 is doped with solder, the upper surface of the lead 1 becomes a wide flat surface 15, as shown in FIG.
Since it consists of a lower flat surface 14 that is slightly lower than this wide flat surface 15 by 0.01 mm, the wide flat surface 15 and the lower flat surface 14 appear to be the same flat surface, and the solder 3 is one lower flat surface 14
It is attached in a raised state in the center, extending from the corner 16 of 1 through the wide flat surface 15 to the corner 16 of the other flat surface 14, which is one level lower.

This is because, as mentioned above, when the lead 1 is viewed cross-sectionally, each corner of the approximately rectangular shape is a right-angled or acute-angled corner, so the amount of solder adhering to the tips of these corners is small. However, it is thought that this is due to the fact that a large amount of solder adheres to the flat surfaces separating the corners in an arcuate cross section due to the action of surface tension.

In addition, the edges of the leads have sharp corners and are not rounded or sloped with obtuse corners at both ends, as in the case of conventional methods, so it is possible to create areas with less solder adhesion. does not have a large area, and the solder discontinuities are only dot-like (linear in the length direction of the lead l).In this case, the solder 3 adheres to the entire circumference of the lead l. To be honest, there may be cases where the amount of solder 3 attached is small at the leading edge of the corner 16.

However, the parts where this solder 3 is not attached are also the four corners of the lead 1 which has a slightly rectangular cross section when viewed in cross section, and each part is only dot-shaped, so the ultra-small transistor of this embodiment The solder depth of lead 1 in 8 is:
It can be scratched better than before.

For this reason, when the ultra-small transistor 8 of the embodiment is surface-mounted, there is sufficient solder around the entire circumference of the fixed part 9 of the lead 1. As shown in FIG. 3 will rise and secure solder fixation will be possible.

Next, the manufacture of such a microtransistor and the lead frame used in its manufacture will be explained.

As shown in the flowchart of FIG. 5, the ultra-small transistor 8 is manufactured through the following steps: lead frame formation, coining, plating, gold foiling, chip bonding, wire bonding, resin molding, solder dipping, and cutting. .

When forming the lead frame, it is made of copper alloy, iron-nickel alloy (4270I), etc., and has a thickness of 0.1 mm to
A thin metal plate of about 0.2 mm is used. In this embodiment, a precision press forms a lead frame 20 having a pattern as shown in FIG. The lead frame 20 includes two frames 21 extending in parallel, a section par 22 connecting the pair of frames 21, and a cantilever type frame extending parallel to the section par 22 from inside the frame 21. It consists of a thin lead 1. The lead 1 has a width of, for example, 0.4 mm. Further, one lead 1 protrudes from one frame 21 and two leads 1 protrude from the other frame 21. One lead 1 of the one frame 21 is located between the two leads 1 of the other frame 21 and serves as a central lead, and its tip is connected to the pair of frames 21 and the adjacent pair of sex bars. 22, and forms a wide tab IO for fixing the chip 12.

Further, the two rods 1 whose tips face on both sides of the tip of the center lead have slightly wider tips, similar to the center lead, and constitute a wire connection portion 11 to which a wire 13 is connected.

Note that the frame 21 is provided with guide holes 23 and positioning depressions 24 used for transporting the lead frame 20 and the like.

Next, in such a lead frame 20, as shown in FIG.
and the upper die 18. Said lower mold 1
7 is a flat surface, but the upper die 18 has a recessed relief part 25 in the center and coining surfaces 26 which are flat surfaces on both sides thereof. This coining surface 26 is adapted to crush (coin) two sagging portions of the lead 1 placed on the lower die 17. That is, as shown in FIG. 9, when the upper mold 18 descends relative to the lower mold 17, the lead 1 is coined by the lower mold 17 and the upper mold 18, so that the droop 2 of the lead 1 is For example, 0.0
It is crushed by 1 mm, and as shown in FIG. 2, a lower flat surface 14 is formed on both sides of a wide flat surface 15. - The lower flat surface 14 is 0.05 mm along the width direction of the lead l.
It is provided over a length of mm to 0.1 mm. On top of this
The burrs 4 are eliminated by the pressing of the lower molds 18 and 17.

Furthermore, the edge of the coining slightly overhangs to the side, as shown in FIGS. 1 and 9, but this is not a problem. In FIG. 10, the sloped lead edge is a coined lead.

Next, the lead frame 20 is plated and the first
As shown by the dots in FIG. 0, the tab 10 and the wire connection part 11 are covered with a plating film 27 made of silver with a thickness of about 3 μm.
28 is formed. This plating is performed, for example, by electrolytic plating or the like after covering the lead frame area that is not to be plated with silicone rubber. As a result, a lead frame 20 having a plating film of 27°28 is manufactured.

Next, as shown by the two-dot chain line in FIG.
0, that is, the surface where the burr 4 exists, as shown in FIG. 11, is 10I! A gold leaf 29 having a thickness of about m is fixed.

Next, the chip 12 is bonded onto the tab 10 of the lead frame 20, as shown in FIG. The chip 12 is carried while being held by vacuum suction by a vacuum suction tool called a collet 30, and is positioned on the gold foil 29 (i!). IIF will be done. The chip 12 is fixed via a eutectic alloy layer 31 of Au-5t.

Next, as shown in FIG. 12, the capillary 32 holding the wire 13 connects the unillustrated electrode of the chip 12 fixed on the tab 10 to the corresponding wire connection portion 11 at the tip of the lead 1. are electrically connected via the wire 13, and the wire 13 is connected to the wire connection portion 1.
1, the wire 13 is held and pulled by a clamper (not shown). As a result, wire 13
The wire fixed to the wire connection part 11 is broken at the root part,
- Tight wire bonding is completed.

In this embodiment, as shown in FIG. 13, two-way wire bonding is performed.

Next, the lead frame 20 that has undergone chip bonding and wire bonding is clamped into a mold die 33 of a transfer mold press, as shown in FIG. The mold 33 consists of a lower mold 34 and an upper mold 35, and a runner 37 through which resin 36 flows when the mold is clamped. Gate 38. Cavities 39 and the like are formed respectively. Therefore, the resin 36 is press-fitted into the cavity 39 through the runner 37, and the resin 36 is hardened by curing the resin.
A package 7 shown in the figures and the like is formed.

Next, the molded lead frame 20 is subjected to a solder dip treatment, and solder 3 is attached to the surface of the lead frame 1 protruding from the package 7, as shown in FIG. At this time, since the solder 3 does not have a rounded edge on the upper surface of the lead 1 and has an acute corner 16, even if the solder 3 does not adhere to the tip of the lead 1, it will stick to the lower flat surface 14 of the lead 1. The solder 3 is attached in an arc shape from the tip of the corner 16 at the end, through the wide flat surface 15, to the corner 16 at the end of the other flat surface 14, which is one step lower. Therefore, even if markings are applied to the surface of the package 7 in the lead frame state or in a state separated from the lead frame to form a single unit and the marks are dried, the lead surface may oxidize or the solder may oxidize due to this heat. There is almost no deterioration of
That is, in the case of this embodiment, since the solder is not thinly applied over a wide area on the lead surface, the solder is not deteriorated by heat. Furthermore, since a small amount of solder is attached to the leading edge of the corner 16, even if the solder at the leading edge deteriorates, oxidation of the lead surface will not occur. Furthermore, this point-like (linear) solder deterioration has almost no effect on solder mounting.

Next, the molded lead frame 20 is taken out from the mold 33, unnecessary lead frame portions are removed by a cutting machine, and the molded lead frame 20 is molded into a superstructure as shown in FIG. A small transistor 8 is manufactured.

In addition, the two-dot chain line that crosses the lead l in FIG.
It shows the cut point of the lead 1.

When mounting such a microtransistor 8, the microtransistor 8 is placed on a predetermined portion of the wiring board 5 made of ceramic or the like, as shown in FIG.

A wiring layer 6 is provided on the main surface of the wiring board 5. Further, on this wiring layer 6, a solder paste layer (solder cream) (not shown) is printed. Therefore, the fixing portion 9 of the lead 1 of the microtransistor 8 is placed on this solder paste layer, and the solder paste layer is melted and hardened by reflow. As a result, the fixing portion 9 of the lead 1 is fixed to the wiring N6 by the solder 3.
The ultra-small transistor 8 will be surface-mounted on the wiring board 5.

During this surface mounting, as shown in FIG. 2, the fixing part 9 of the lead 1 is corrected by coining and the solder depth is well formed, so that the fixing part 9 of the lead 1 is not attached to the lead 1 first. When the solder and the solder cream on the wiring layer 6 are melted by heat, the solder does not break off at the upper edge of the lead 1, and as shown in FIG. 4 and FIG. is covered with sufficient solder 3, allowing reliable soldering.

According to such an embodiment, the following effects can be obtained.

(1) In the ultra-small transistor of the present invention, the leads that protrude from the package and extend in a step-like manner are corrected by coining, so that the solder is applied to the entire circumference. The effect of being deepened over the area can be obtained.

(2) According to (1) above, the ultra-small transistor of the present invention has solder already attached to the entire circumference of the leads and the solder has not deteriorated, so that the solder does not easily cover the leads during surface mounting. Since the lead is sucked up, the entire circumference of the lead is covered with a sufficient amount of solder, resulting in reliable soldering.

(3) Due to the above (2), the ultra-small transistor of the present invention can be soldered reliably, so that the reliability of mounting can be increased.

(4) In the lead frame of the present invention, the sagging portion caused by pressing is formed into a lower flat surface by coining, so that the lead frame has a structure with sharp corners on both edges of the upper surface of the lead. Solder also adheres to the entire upper surface of the lead, producing the effect that the entire circumference of the lead is covered with solder.

(5) According to the above (4), the semiconductor device using the lead frame with good solder dip property according to the present invention has an effect of high mounting performance.

(6) According to the above (1) to (5), according to the present invention, surface mounting by soldering can be performed with good reproducibility, so it is possible to improve the mounting yield of semiconductor devices, and to improve the mounting yield of electronic devices incorporating semiconductor devices. A synergistic effect of increasing credibility can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, V
Even if coining is performed using an upper mold having a shape of a letter protrusion and a corner portion 16 with an acute tip is provided on the outside of the figure 7 depression 40 as shown in FIG. 17, the solder dip property of the lead 1 can be improved. can be achieved. Further, in this structure, since the solder accumulates in the ■-shaped recess 40, the adhesion of the solder 3 to the upper surface of the lead 1 also becomes better.

In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to the manufacturing technology of ultra-small transistors, which is the field of application that formed the background of the invention, but it is not limited thereto. It can also be applied to manufacturing technology for semiconductor devices.

The present invention is applicable to at least a technology for manufacturing semiconductor devices having a structure in which solder is attached to leads by a solder dip.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In the semiconductor device of the present invention, the sagging portion of the υ''-domain is corrected by coining, and solder is adhered to the surface metal area between the corner portions of both edges caused by the correction.

For this reason, the solder adheres to the entire circumference of the leads, so when a semiconductor device is mounted on a wiring board, the solder adhered to the leads and the solder cream provided on the bottom side of the leads are damaged by heat. Melt and become one. Since the surface of the lead frame is not oxidized, the integrated solder is easily absorbed to the top surface of the leads.

As a result, the entire circumference of the lead is covered with solder, so that solder fixation can be performed reliably and with high reliability.

Further, electronic equipment incorporating the semiconductor device of the present invention has a high reliability.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a part of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged sectional view of a lead, FIG. 3 is a perspective view of the semiconductor device in an inverted state, and FIG. Similarly, a perspective view showing the mounting state of the semiconductor device, FIG. 5 is a flowchart showing the manufacturing method of the semiconductor device, and FIG. 6 is a plan view showing the lead frame used in manufacturing the semiconductor device of the present invention. Similarly, FIG. 8 is an enlarged sectional view showing the lead portion of the lead frame, FIG. 8 is an enlarged sectional view showing the coining process applied to the lead sag, FIG. 9 is an enlarged sectional view showing the coined lead, and FIG. 10 is an enlarged sectional view showing the coined lead. FIG. 11 is a sectional view showing the chip bonding state; FIG. 12 is a sectional view showing the wire bonding state; FIG. 13 is the same resin molded state. 14 is a plan view showing a lead frame in a molded state; FIG. 15 is a sectional view showing a mounted semiconductor device; FIG. 16 is an enlarged sectional view showing a lead in a soldered state. , FIG. 17 is an enlarged sectional view of a lead according to another embodiment of the present invention, FIG. 18 is a perspective view showing a defective state in conventional semiconductor device adhesive flow mounting, and FIG. 19 similarly shows a defective state in reflow mounting. 20 is a cross-sectional view of the lead with a defective solder dip. 1...Lead, 2...Who, 3...Solder, 4...
・Paris, 5... Wiring board, 6... Wiring layer, 7...
Package, 8... Ultra-small transistor, 9... Fixed part, 10... Tab, 11... Wire connection part, 12
...Chip, 13...Wire, 14...-lower flat surface, 15...Wide flat surface, 16...Corner, 17
... lower mold, 18 ... upper mold, 20 ... lead frame, 21 ... frame, 22 ... section bar, 23.
...Guide hole, 24...Positioning depression, 25...
Relief part, 26... Coining surface, 27° 28... Plating film, 29... Gold leaf, 30... Collet, 31.
... Eutectic alloy layer, 32... Capillary, 33... Mold mold, 34... Lower mold, 35... Upper mold, 36...
・Resin, 37...Runner, 38...Gate, 3
9...Cavity, 40...V-shaped recess.

Claims (1)

[Claims] 1. A surface-mounted semiconductor device comprising a package and leads protruding from the periphery of the package, the leads being formed by punching out a metal plate. . A surface-mounted semiconductor device, characterized in that the sagging portion of the edge of the lead due to punching is corrected by coining so that the edge has a corner portion. 2. A lead frame formed by pressing a metal plate and having a tab for fixing a semiconductor element to the main surface and a lead whose tip is exposed around the tab,
A lead frame characterized in that at least the sagging portion of the lead caused by the green pressing is corrected by coining so that the lead frame has a structure having a corner portion at the edge.