JPH01128563A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To largely improve the integration of a dynamic semiconductor memory by providing a memory cell containing first and second grooves of 2-stage configuration, a second conductivity type semiconductor layer connected to bit lines, a capacity element having a conductive filler as a storage node, and first and second transfer gate electrodes. CONSTITUTION:A memory cell which has first and second grooves dug from the surface of a P-type single crystalline silicon substrate 101 toward its interior, an N-type semiconductor layer 104 connected to bit lines 202, a capacitor element having a conductive filler 106 made of polycrystalline silicon as a storage node, a first transfer gate electrode 103(made of polycrystalline silicon) connected to a word line 206, and a second transfer gate electrode 102(made of polycrystalline silicon) connected to a control signal line 204 disposed in parallel with the bit line 202 is provided. A pair of bit lines 202, 203 connected to a sense amplifier 201 are folded through the amplifier 201 and disposed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a dynamic semiconductor memory.

[Conventional technology]

As shown in FIG. 3, a conventional memory cell of this type of memory consists of one capacitive element 301 and one transfer gate 302. Its operation will be briefly explained as follows.

In the dynamic memory, whether or not a charge is stored in the capacitive element 301 corresponds to the information "l" or I'0.Now, the transformer 2 argate 302 t-nMO
8) Assuming that the state where charge is stored is 1" and the state where no charge is stored is 0", for example, to store 11", node 304
'i Keep the potential higher than the ground potential, nMO8
) Node 303 connected to the gate electrode of the transistor
f:nMO8) When the voltage is made higher than the threshold voltage of the transistor 302, charge flows into the capacitive element 301 and information 1'' is stored.

[Problems with conventional technology]

Conventional memory cells have the disadvantage that when a semiconductor memory device is configured with 7 all dead bit lines, the degree of integration cannot be increased as compared to an open bit line configuration.

A detailed explanation is as follows. The folded bit line configuration refers to a pair of bit lines 30 as shown in FIG.
5 and 306t - is folded back via the sense amplifier 307, and the open bit line configuration is 81!5
As shown in the figure, a pair of bit lines 308 and 309t' are extended on both sides of the sense amplifier 3070. Therefore 7
In an all-dead bit line configuration, each memory cell 310-3 is connected to a bit line coming out of one sense amplifier.
14 must be placed one space apart from the intersection of the word line 319 and the bit line, but in an open bit line configuration, it can be placed for each memory cell gold word line 320. That is, the memory cell pitch in the bit line direction is 7.
In the case of an all-dead bit line configuration, 2 of the word line pitch
In the case of an open bit line configuration, it is equal to the word line value, and in general, an open bit line configuration has a higher degree of integration than a folded bit line configuration.

However, although it is inferior in terms of integration, the folded bit line configuration has the advantage that malfunctions are less likely to occur during signal reading or writing.

In other words, in an open cell) ff configuration, for example, if only one bit line is 10" and all other bit lines are 11", this 10" bit line is separated from the other 1" bit lines. While it is easy to accidentally read and write @l”e when receiving interference, in the case of a folded bift line, 1
If the real bit line 305 is '0', the sense amplifier 30
The bit line 306 that goes through all 7 and turns back is ``1''
Therefore, the bit lines connected to one sense amplifier 307 are a combination of 1'' and @0'', which has the effect of canceling out interference from other bit lines. These effects become more pronounced as the degree of integration increases and the bit line spacing decreases. By the way, 7 all debt line j
In the # structure, it was explained that the memory cell pitch in the bit destruction direction is twice the word line pitch, resulting in a lower integration density than the open bit line structure, but if the capacitance included in the memory cell has a planar structure, this problem is considerably solved. It can be avoided.

That is, FIG. 6 shows a plan layout diagram of an example of the elements of a dynamic memory cell, and since the capacitive element 322 shown surrounded by a dotted line is placed next to the transformer 7 argate 321 shown surrounded by a broken line, If the word line 323 of the transfer gate of the memory cell is disposed on the capacitive element 322 via an interlayer insulating film, the degree of integration is almost determined by the size of the memory cell and is not affected much by the word line pitch.

A further advantage of the folded bit line configuration is that the pitch of the sense amplifiers is looser than that of the open bit line configuration. The reason is 7 as shown in Figure 4.
In the all-dead bit line configuration, one sense amplifier is placed for two rows of memory cells, whereas in the open bit line configuration, one sense amplifier is placed for each row of memory cells, as shown in Figure 5. This is because a sense amplifier is placed there.

For the reasons explained above, in the conventional dynamic memory, the best method was to use a folded bit line configuration.

However, in recent years, as memory has become more densely integrated,
It has been proposed that memory cells have a three-dimensional structure, and some products (such as Nio) have already used memory cells with a three-dimensional structure. In some cases, the degree of integration of a memory device cannot be increased very much with a folded bit line configuration like this.The reason for this is explained in the IETM Technical Digest (
IEDM Technical Digest) magazine,
This will be explained using the TTC cell published on pages 714 to 717, December 1985.

As shown in Figure 7, a TTC cell has a capacitance, polycrystalline silicon 326 is used as a part of the electrode in a groove formed in a semiconductor substrate 324, polycrystalline silicon 325 is used as a gate electrode, and an impurity diffusion layer 327 is used. and 328 gold source area, respectively.
MIS type F with transformer 7 argate as drain region
ET'i is being built. FIG. 8 shows a plan layout diagram when this array of TTC cells is arranged in an open bit line configuration, but if this is arranged in a folded bit line configuration, memory cells 329 are lined up every other memory cell. As a result, the degree of integration of the memory cell array section is reduced to about 1/2 of the open bit IVil configuration.

[Problem t--Means for Solving] 'The semiconductor memory device of the present invention includes a 1.42nd groove of a two-stage structure dug inward from the surface of a first conductivity type semiconductor substrate; a second conductivity type semiconductor layer selectively provided above or near the first groove on the surface side of the semiconductor substrate and connected to the bit line; a capacitive element whose storage node is a conductive filler buried through the body; ml transfer gate electrode connected to the insulating film, provided on the surface of the second groove side of the insulating film,
a memory cell including a second transfer gate electrode connected to a control signal line arranged in parallel with the bit line, and a pair of bit lines connected to a sense amplifier are looped back via the sense amplifier. They are arranged parallel to each other.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a memory cell showing the main parts of an embodiment of the present invention, and FIG. 2 is a circuit diagram of the embodiment.
- In this embodiment, first and second grooves are dug inward from the surface of a P-type single crystal silicon substrate 1010 and have a configuration of 92 steps, and
The N-type semiconductor layer 104 is selectively provided above or near the first groove on the surface side of the single crystal silicon substrate 101 and is connected to the bit line 202, and the +g2 groove is formed on the surface of the N-type semiconductor layer 104. dielectric (silicon oxide film 108) provided on
Conductive filler 10 made of polycrystalline silicon filled through
6 as a storage node, and an N-type semiconductor layer 1 of silicon oxide 11109 provided on the side surface of the first groove described above.
The first transfer gate electrode 103 (made of polycrystalline silicon) is provided on the surface of the silicon oxide film 109 and connected to the word line 206, and the first transfer gate electrode 103 (made of polycrystalline silicon) is provided on the surface of the silicon oxide film 109 on the second groove side and is connected to the word line 206. arranged parallel to line 202 t
It has a memory cell including 42 transfer gate electrodes 102 (made of polycrystalline silicon) connected to a control signal IfA 204, and a pair of bit lines 202 and 203 connected to a sense amplifier 201 form a sense amplifier 201't.
- and are arranged parallel to each other.

To explain the manufacturing method of this example, after the entire TTC cell is formed on the P-type single crystal silicon base &101, a part of the polycrystalline silicon which is the second transfer gate electrode 102 is selectively etched by photolithography and anisotropic etching. In this case, polycrystalline silicon can be filled in as the electrode 103 of the first transformer by removing part of the first groove.

1st. Second transformer 7 agate voltage 1fIA102 and 1
When the voltage on both edges of 03 becomes higher than the threshold voltage, the N-type semiconductor layers 104 and 105 are electrically connected by the inversion layer, and the polycrystalline silicon (106), which is the electrode of capacitor 1, is connected to the sense amplifier. be done. However, 107 is a thick silicon oxide layer for electrically insulating the memory cell and other memory cells.

In the next section, the operation of this embodiment will be explained.

If the word line 206 is now made higher than the threshold voltage, the gate electrode will be connected to it nM08) transistor 210,
211 are all turned on. However, the control line 20
If only the capacitive element 4 is set higher than the threshold voltage and the control signal line 205 is set lower than the threshold voltage, only the capacitive element -PQO9 is connected to the sense amplifier 201, and the capacitive element 2 is connected to the sense amplifier 201.
14 is not connected, and only memory cell 207 is selectively selected.

The present invention is an MIS type FET with two transfer gates.
This is different from the prior art in that the memory cells are accessed by logical product (positive logic) of two signal lines.

That is, the bit line 2 that is turned back at the sense amplifier 201
By arranging two control signal lines 204 and 205 in parallel with 02 and 203, and performing an AND between these 204 and 205 and the word line 206, the transfer gate gold included in each memory cell 207 and 208 is turned on. , for example, word line 206 and control signal line 2
If the control signal line 205'i@0'' is set with 04 as the first'', the memory cell 207 will be accessed, but the memory cell 208 will not be accessed. Therefore, the memory cells can be arranged with the same pitch as the open bit line configuration, but the operation is similar to the folded bit line configuration, and the sense amplifier pitch of the folded bit line configuration is looser and is susceptible to interference from other bit lines. While it has the advantage of being difficult to use, it also has the advantage of having a high degree of integration in the memory cell array section with an open bit line configuration. Of course, since the memory cell of the present invention is a two-transistor, one-capacitor type, it can be said that the degree of integration will not increase if we consider the planar type that is commonly seen in the past. , the area occupied on the plane is equal to that of the one-transistor-one-capacitance method. However, in the present invention, the human line 202. Word line 206. The control signal pa2o4 and three independent signal wirings are required for one memory cell, which may make it difficult to manufacture memory devices, but recent semiconductor devices have multilayer wiring with three or more layers. has become almost common,
The present invention is fully possible to implement.

〔Effect of the invention〕

As explained above, the present invention has the advantage that the sense amplifier pitch of the folded bit line configuration is loose and that it is less susceptible to interference from other pitch lines, and at the same time, the integration density of the memory cell array part of the open bit configuration is reduced. Since it also has the advantage of high performance, it has the effect of greatly improving the integration density of a dynamic semiconductor memory device.

[Brief explanation of the drawing]

(Figure 1 is a sectional view of a memory cell showing the main parts of an embodiment of the present invention, Figure 2 is a circuit diagram of an embodiment, and the third factor is 1 to 2.
Figure 4 is a circuit diagram of a 7-way single-capacity memory cell, Figure 5 is a circuit diagram of an open bit line type memory, and Figure G6 is a memory showing the main parts of a conventional example. FIG. 7 is a sectional view of the T'l'C cell, and FIG. 8 is a plan layout diagram of the TTC cell. 101...P-type wheel crystal silicon substrate, 102...
...Second transfer gate electrode, 103...
...First transfer gate 1i! pole, 104
, 105... N-type medium conductor layer, 106...
・Conductive optical filler. 107.108,109...Silicon oxide film, 2
01...Sense amplifier, 202, 203...
...Bit line, 204.205...Control signal line, 206...Word line, 207,208...
...Memory cell, 209...Capacitive element, 210
,211,212,213...nM08) U/
transistor, 214... capacitive element, 301...
...YongJt*child, 302...Transfer Kate, 303.304...Node, 305,
306... Bit line, 307... Sense amplifier, 308, 309... Bit line, 31
0-318...Memory cell, 319.320
...word line, 321...transfu game), 322...capacity, 323...
・Word line, 324...Semiconductor substrate, 325,
326...Polycrystalline silicon, 327,328...
...Impurity diffusion L329...Memory cell, 330...Bit line, 331...Word line. Agent Patent Attorney Shinmu Uchihara 1 Cabinet 2 z 3 Figure 14

Claims (1)

[Claims] First and second grooves having a two-stage configuration dug inward from the surface of the first conductivity type semiconductor substrate, and selectively provided above or near the first groove on the surface side of the semiconductor substrate. is,
a second conductivity type semiconductor layer connected to the bit line;
a capacitive element whose storage node is a conductive filler that fills a groove through a dielectric provided on its surface; and a side of the second conductivity type semiconductor layer of an insulating film provided on a side surface of the first groove. a first transfer gate electrode provided on the surface of the insulating film and connected to the word line; and a first transfer gate electrode provided on the surface of the insulating film on the second groove side and connected to a control signal line arranged parallel to the bit line. A semiconductor memory comprising a memory cell including a second transfer gate electrode, wherein a pair of bit lines connected to a sense amplifier are folded back and arranged in parallel via the sense amplifier. Device.