JPH01132123A - Method for forming resist pattern - Google Patents

Abstract

PURPOSE:To provide good resolution and prevent the thinning of the pattern width by forming an ion-implanted layer in the region of a flattened resist where a resist pattern is to be formed, and etching the flattened resist using the ion-implanted layer as a mask. CONSTITUTION:After applying a flattened resist 1 on a substrate 2, a patterning layer 6 is formed on the flattened resist 1, and the region where a resist pattern is to be formed is exposed. Then, by use of the patterning layer 6 as a mask, ions are implanted, so as to form an ion-implanted layer 8 in the region where the resist pattern is to be formed. Thereafter, the patterning layer 6 is removed, and by use of the ion-implanted layer 8 as a mask the flattened resist is etched, thereby forming a resist pattern 11 on the substrate 2. For instance, the ion implantation is of Si ions 7, and the concentration of the implantation is 10<17>ions/cm<2> or more. The etching of the flattened resist 1 is performed by a O2 plasma reactive ion etching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resist pattern forming method, and particularly to a resist pattern forming method for forming a resist pattern in a submicron region on a substrate.

[Prior Art] In a semiconductor device manufacturing process, a step of forming a resist pattern in a submicron region is essential. FIGS. 2A, 2B, and 2C are cross-sectional views showing the steps of a conventional resist pattern forming method.

A conventional resist pattern forming method will be described with reference to these figures.

A resist 1 is applied onto a semiconductor substrate 2 by a spin coating method (FIG. 2A).

Next, using the mask 5, ultraviolet light 3 is irradiated by an exposure device (not shown). Then, a photosensitive layer 4 is generated in the resist 1 (FIG. 2B).

Next, in a developing step, the photosensitive layer 4 is dissolved with an alkaline solution to form a resist pattern 11 (FIG. 2C).

[Problems to be Solved by the Invention] The conventional resist pattern forming method is configured as described above. However, as shown in FIG. 3A, there is a problem in that when the developing process approaches the resolution limit, poor resolution occurs.

Further, in order to increase the resolution, it is necessary to increase the amount of UV irradiation light, but in this case, there is a problem that the pattern width narrows as shown in FIG. 3B. Both of these problems are problems when forming a resist pattern in the submicron region on a substrate, and the resulting resist pattern is not suitable for practical use.

This invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a resist pattern forming method that provides good resolution and does not cause narrowing of the pattern width.

[Means for Solving the Problems] The present invention relates to a resist pattern forming method for forming a resist pattern in a submicron region on a substrate. And, it is characterized by including the following steps.

(a) A step of applying a flattening resist onto the substrate.

(b) A step of forming a patterning layer on the planarized resist and exposing a region where the resist pattern is to be formed.

(C) A step of forming an ion implantation layer in a region of the flattened resist where the resist pattern is to be formed by implanting ions using the patterning layer as a mask.

(d) Thereafter, the step of removing the patterning layer and etching the flattened resist using the ion implantation layer as a mask to form a resist pattern on the substrate.

[Operation] Since the planarized resist is etched using the ion-implanted layer formed on the planarized resist as a mask, a resist pattern with good resolution and no pattern thinning can be formed.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1A, 1B, 1C, and 1D are sectional views showing the steps of an embodiment of the present invention.

A planarization resist 1 is applied onto a semiconductor substrate 2.

Then, a patterning layer 6 is formed thereon to expose a region where a resist pattern is to be formed (FIG. 1A).

Next, using the patterning layer 6 as a mask, ions are implanted into the entire surface, for example, Si+ ions 7 are implanted at a high concentration.

The preferred injection amount is 1017 particles/Cm2 or more. By this ion implantation, an ion implantation layer 8 is formed in the region of the flattened resist 6 where a resist pattern is to be formed (
(FIG. 1B) Next, only the patterning layer 6 is removed (FIG. 1C).

Next, when reactive ion etching is performed using oxygen gas 9 in the state shown in FIG. Then, this 5i02 film 10 serves as a mask, and the resist layer 1 below the SiO□ film 10 is no longer etched.

On the other hand, the areas not masked by the ion implantation layer 8 are
It is decomposed by the 0+ ions 9, forming a pattern 11 with good resolution as shown in FIG. 1D.

In this embodiment, the resist pattern 11 is an inversion of the first mask. Furthermore, by setting the width of the ion implantation layer 8 wide during patterning (as shown in FIG. 1A), it is possible to form a resist pattern 11 that is thicker than the mask dimension.

In the above embodiment, the case where Si+ ions were used as the implanted ions was explained, but the present invention is not limited to this, and it is possible to form a layer having resistance to 0□ plasma reactive ion etching. If so, other ions may be used. For example, Al.

Metal ions such as 1 ion are also preferably used.

The implanted ions are A1. In the case of + ions, the ion implantation layer 8 is a layer of AQ, zOs.

[Effects of the Invention] As explained above, according to the present invention, an ion-implanted layer is formed in the region of the planarized resist where a resist pattern is to be formed, and the planarized resist is formed using the ion-implanted layer as a mask. Since etching is performed, a resist pattern with good resolution and no pattern thinning is formed. Therefore, even when a resist pattern in the submicron region is formed on a substrate, a practical resist pattern can be formed.

[Brief explanation of the drawing]

FIGS. 1A, 1B, 1C, and 1D are sectional views showing the steps of an embodiment of the present invention. FIGS. 2A, 2B, and 2C are cross-sectional views showing the steps of a conventional resist pattern forming method. FIGS. 3A and 3B are cross-sectional views of a resist pattern generated when a resist pattern in a submicron region is formed on a substrate by a conventional resist pattern forming method. In the figure, 1 is a planarization resist, 2 is a semiconductor substrate, and 6 is a flattened resist.
7 is a patterning layer, 7 is a silicon implanted ion, 8 is an ion implantation layer, 9 is an O+ ion, 10 is a 5in2 film, and 11 is a resist pattern. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A resist pattern forming method for forming a resist pattern in a submicron region on a substrate, which comprises the steps of: applying a planarizing resist on the substrate; forming a patterning layer on the planarizing resist; a step of exposing a region where a resist pattern is to be formed; a step of forming an ion implantation layer in a region of the flattened resist where the resist pattern is to be formed by implanting ions using the patterning layer as a mask; A method for forming a resist pattern, comprising: thereafter removing the patterning layer, etching the flattened resist using the ion implantation layer as a mask, and forming a resist pattern on the substrate. (2) The resist pattern forming method according to claim 1, wherein the ion implantation is Si ion implantation, and the implantation concentration is 10^1^7/cm^2 or more. (3) The resist pattern forming method according to claim 1 or 2, wherein the planarized resist is etched by O_2 plasma reactive ion etching.