JPH01133346A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify a manufacturing process, by utilizing the diffusion process of an isolation region so as to form the lower electrode of MIS type capacity and introducing P-type impurities into the surface of a lower electrode region as well immediately before depositing a nitriding film. CONSTITUTION:Simultaneously with the formation process of isolation regions 24, a lower electrode region 26 of MIS type capacity is formed and the oxide film 28 of the surface of the lower electrode region 26 is partially exposed by patterning its film. Then, P-type impurities are introduced selectively by utilizing this pattern and a dielectric thin film 29 is formed at the surface of the exposed lower electrode region 26. And then, after forming this thin film 29, an emitter region 30 of an NPN transistor is formed by diffusion. In this way, the isolation regions 24 are utilized as the lower electrodes of MIS type capacity and deposition of a nitriding film is performed prior to the emitter diffusion process and then, heat-treatment which makes hFE of the NPN transistor disperse after forming the emitter region 30 can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an NPN transistor glue for a semiconductor integrated circuit incorporating an MIS type capacitive element. This invention relates to a manufacturing method that facilitates control.

(b) Conventional technology Bipolar IC is a vertical NPN in which a base and an emitter are double-diffused on the surface of a semiconductor layer that serves as a collector.
It is mainly composed of transistors. Therefore, the base and emitter diffusion processes for manufacturing the NPN transistor are essential processes, as well as the high-concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction isolation process for each element. This is an essential process (basic process) for manufacturing bipolar ICs, along with the isolation region forming process and the electrode forming process for electrical connection.

On the other hand, due to circuit requirements, there is a demand for incorporating other elements such as PNP transistors, resistors, capacitors, Zener diodes, etc. on the same substrate. In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since various conditions for the base and emitter diffusion steps are set with the most important consideration given to the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter diffusion steps using only the basic steps. Therefore, basic NP
A new process may be added not for the purpose of forming an N transistor but for the purpose of incorporating other elements or improving the characteristics of other elements. For example, a P+ diffusion process to form an anode region that controls the Zener voltage of the Zener diode with the cathode region by the emitter diffusion, an R diffusion process to form a resistance region with a different resistivity from the base region, and implant resistance formation. These include the process of forming a nitride film to form a nitride film capacitor that provides a larger capacitance than that of the MOS type, and the process of forming a low-resistance region on the left to further reduce the collector series resistance of an NPN (NPN) transistor. This is a step (optional step) in which it can be determined whether or not to add the IC based on consideration of the use, purpose, and cost of the IC.

FIG. 3 shows an MIS type capacitor formed using the above optional process. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, (3) is an N+-type buried layer, (4) is a P+-type isolation region, (5) is an island, (
6) is an N" type lower electrode region formed by emitter diffusion, (7)
) is a silicon nitride film (S1sN) as a high dielectric constant insulator.
4), (8) are upper electrodes made of aluminum material, (
9) is an oxide film, and (10) is an electrode.

Incidentally, an MIS type capacitor using a nitride film is described in, for example, Japanese Patent Laid-Open No. 60-244056.

(c) Problems to be solved by the invention However, the conventional MIS type capacitor uses N as the lower electrode.
Since the emitter region of a PN transistor is used, a nitride film must be formed after depositing an N-type impurity for forming the emitter region, and then drive-in of the N-type impurity is performed. 80 used for
Heat treatment at around 0°C diffuses the emitter region, so N
There was a drawback that the hrt (current amplification factor) of the PN transistor varied widely, making it difficult to control.

In addition, it is necessary to change the heat treatment conditions for the emitter region depending on whether or not an optional process necessary for forming the nitride film is added, so process management is required for each model, and there is a drawback that management cannot be standardized. Ta.

(d) Means for solving the problems The present invention was made in view of the disadvantages of the separation area (24
) at the same time as the formation process of the lower electrode region (2) of the MIS type capacitor.
6), a step of patterning the oxide film (28) on the surface of the lower electrode region (26) and partially exposing it, and a step of selectively introducing P-type impurities using the pattern. , forming a dielectric thin film (29) on the surface of the exposed lower electrode region (26);
9) After forming the emitter region of the NPN transistor (
30).

(*) Function According to the present invention, since the isolation region (24) is used as the lower electrode of the MIS type capacitor, the nitride film can be deposited before the emitter diffusion process, and the emitter region (30)
It is possible to eliminate heat treatment that would cause variations in the adhesive quality of the NPN transistor after formation.

Furthermore, since the P-type impurity is ion-implanted or deposited using the oxide film pattern for nitride film (SijNa) deposition, the resistance component of the lower electrode region (26) under the dielectric thin film (29) can be reduced.

(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (
The surface of the N+ type buried layer (22) is selectively doped with N type impurities such as antimony (Sb) or arsenic (As).
), and an N-type epitaxial layer (23) with a thickness of 5 to 10 μm is laminated on the entire surface of the substrate (21).

Next, as shown in FIG. 1B, by selectively diffusing poron (B) from the surface of the substrate (21), the buried layer (22
A P+ type isolation region 24 passing through the epitaxial layer (23>) is formed so as to surround each of the epitaxial layers (23). Separation area (
The epitaxial layer (23) surrounded by 24) becomes an island (25) for forming each circuit element. At the same time, the poron (B) in the separation region (24) diffusion process is also diffused into the region corresponding to the buried layer (22) on the surface of the island (25), and the buried layer (2) is diffused from the surface of the epitaxial layer (23).
A lower electrode region (26) is formed that reaches 22). The isolation region (24) is formed by saturated diffusion and penetrates the epitaxial layer (23), so the impurity concentration on its surface is 10.
It will be around "atoms-cm-". Further, the bottom of the lower electrode region (26) is formed so as to be in contact with the buried layer (22), and the lower electrode region (26) is formed by the buried layer (22).
is electrically insulated from the ground potential of the substrate (21).

Therefore, since the MIS type capacitor is electrically independent, there are no restrictions on the circuit configuration.

Next, as shown in FIG. 1C, poron (B) is selectively ion-implanted or diffused into the surface of an island (25) different from the island (25) on which the lower electrode region (26> is formed) to form an NPN. A base region (27) that will become the base of the l-transistor is formed.After that, an oxide film (28) is formed on the surface of the epitaxial layer (23) by thermal oxidation or CVD.
), and using positive or negative photoresist, form an oxide film pattern having openings on a part of the surface of the lower electrode region <26>, and using this oxide film pattern, form a lower electrode. Poron (B) is ion-implanted or deposited selectively on the surface of the region (26). In this step, the impurity concentration of poron (B) on the surface of the lower electrode region (26) was reduced to 10"a
Improve to around toms-cm-'. Therefore, the resistance component of the lower electrode region (26) can be reduced.

Next, as shown in the first diagram, a silicon nitride film (SisNa) is deposited on the entire surface of the epitaxial layer (23) to a thickness of several hundred to several thousand layers using techniques such as atmospheric pressure CVD, and then dry etched etc. The exposed lower electrode region (2
A dielectric thin film (29) is formed to cover the surface of 6). Silicon nitride film (sist'ia) is silicon oxide film (Si
Since it exhibits a higher dielectric constant than Ox), it is possible to form a large capacity. Thereafter, an oxide film (28) is deposited by CVD so as to cover the dielectric thin film (29).

Next, as shown in FIG. 1E, holes are opened in the oxide film (28) on the surface of the base region (27) and the surface of the island (25) of the NPN transistor, and using this oxide film (28) as a mask, ) by selectively diffusing N4 type emitter region (30) and collector contact region (31).
form.

Next, as shown in FIG. 1F, a resist pattern of negative or positive photoresist is formed on the oxide film (28), and the oxide film (28) on the dielectric thin film (29) is removed.
Oxide film (28) by wet or dry etching
A contact hole for electrical connection is formed in a desired portion of the wafer. Then, an aluminum layer is formed on the entire surface of the substrate (21) by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned again to form an electrode (32) of a desired shape and an upper electrode (3) on the dielectric thin film (29).
3) Form.

According to the manufacturing method of the present invention, since the diffusion process of the separation region (24) is used to form the lower electrode of the MIS type capacitor, there is no need for any additional process to form the lower electrode of the MIS type capacitor. In addition, the manufacturing process of the dielectric thin film (29) can be placed before the emitter diffusion process. Then, between the deposition of phosphorus (P) for forming the emitter region (30) and the drive-in of phosphorus (P), the MIS
There is no need to perform heat treatment to form mold capacitance, and N immediately changes from the state in which phosphorus (P) is initially diffused by depositing.
A heat treatment (drive-in) process can be performed to control the hrt (current amplification factor) of the PN transistor. Therefore, NPN transistor glue.

, and the difficulty in controlling h□ caused by incorporating the MIS type capacitor can be solved. Also,
Since the heat treatment conditions for the emitter region (30) can be unified for models that incorporate MIS type capacitors and models that do not, process management for each model becomes extremely easy.

Furthermore, a lower electrode region (26) is formed immediately before the nitride film deposition.
Since P-type impurities are introduced into the surface, the resistance component of the lower electrode can be reduced, and the voltage dependence, frequency dependence, and hysteresis characteristics of the MIS type capacitance can be reduced. Moreover, since the P-type impurity is introduced using the oxide film pattern for forming the dielectric thin film (29), the process can be simplified.

The present invention is not limited to the embodiment shown in FIG. 1, but can also be applied to semiconductor integrated circuits using upper and lower separation techniques. moreover,
In the case where the upper and lower separation technology is used, instead of using both the upper and lower areas, the upper and lower separation areas (
It is also conceivable to form the lower electrode region (26) using only the upper diffusion layer (35). In this case, since the lower electrode region <26) does not reach the buried layer (22), electrical insulation from the substrate (21) can be achieved.

(g) As described in detail, according to the present invention, there is almost no variation in h□ of the NPN transistor due to the addition of the MIS type capacitor as an optional device (7), and the hrt of the NPN transistor is The present invention has the advantage of providing a method for manufacturing semiconductor integrated circuits that is extremely easy to control. In addition, the processing conditions for the emitter region (30) can be unified for models that incorporate MIS type capacitors and models that do not.
It has the advantage that process control for each model can be simplified, and furthermore, wafers of different models can be heat-treated in the same diffusion furnace, making it possible to produce multiple models in small quantities.

Since a P-type impurity is introduced into the surface of the lower electrode region (26) immediately before nitride film deposition, a MIS type capacitor with good characteristics and small voltage dependence and hysteresis can be incorporated, and it can be used for forming the dielectric thin film (29). Since the impurity is introduced using the oxide film pattern, it also has the advantage of simplifying the process.

[Brief explanation of the drawing]

1A to 1F are sectional views for explaining the present invention, FIG. 2 is a sectional view for explaining a second embodiment of the invention, and FIG. 3 is for explaining a conventional example. FIG. (21) is a P-type semiconductor substrate, (26) is the lower electrode region of the MIS type capacitor, (27) is the P-type base region of the NPN transistor, (29) is the dielectric thin film, (30)
is the N1 type emitter region of the NPN transistor, (33
) is the upper electrode of the MIS type capacitor.

Claims (1)

[Claims] (1) forming a buried layer of the opposite conductivity type in a desired region of a semiconductor substrate of one conductivity type; forming an epitaxial layer of the opposite conductivity type on the substrate; A step of selectively diffusing impurities to form isolation regions to form a plurality of islands, and at the same time forming a lower electrode region of a MIS type capacitor of one conductivity type on the surface of one island; a step of forming a base region of one conductivity type of a vertical bipolar transistor, a step of exposing a part of the surface of the lower electrode region and selectively introducing impurities of one conductivity type, a surface of the exposed lower electrode region; a step of depositing and forming a dielectric thin film of the MIS type capacitor, and a step of forming an emitter region of a vertical bipolar transistor by selectively diffusing impurities of opposite conductivity type after forming the dielectric thin film. , forming a conductive film on the entire surface, providing an upper electrode of the MIS type capacitor on the dielectric thin film, and providing electrodes in ohmic contact with each region in desired regions. A method for manufacturing a semiconductor integrated circuit.