JPH011380A - Luminance signal processing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video tape recorder (hereinafter referred to as 1'-VTRJ).
The present invention relates to an m+1 signal processing circuit for use in magnetic recording/reproducing systems such as (referred to as "m+1").

2. Description of the Related Art In recent years, attempts have been made to improve image quality in the fields of television receivers and VTRs.

Hereinafter, a vertical emphasis circuit, which is an example of the above-mentioned conventional VTR image quality improvement technique, will be explained with reference to the drawings.

In FIG. 2, l is a 1H delay line, the output of which is connected to the first coefficient 'a2 with coefficient . The output side of the first coefficient multiplier 2 is connected to the first adder 3, and the first adder 3 adds the input signal from the input terminal 4 and the output of the first coefficient multiplier 2. , outputs the result to the 1H delay line 1.

The output side of the 1H delay line 1 is also connected to the second coefficient multiplier 5,
This second coefficient unit 5 has a coefficient (1-).

6 is a subtracter, and the output of this second coefficient multiplier 5 and the input terminal 4
Take the difference with the input signal from
It outputs to the i-device 7. The third coefficient unit 7 has a coefficient x and is connected to the limiter 8.

A second adder 9 adds the output of the limiter 8 and the input signal from the input terminal 4 and outputs the result.

The operation of the conventional vertical emphasis circuit configured as described above will be described below. first,
During recording, an input signal is input from the input terminal 4, passes through the lH delay line and the first coefficient book 2, and is added to the original input signal in the first adder 8, thereby creating a low-pass signal in the vertical direction. Can be filtered. After passing the output of this low-pass filter through a second coefficient unit 5, a subtracter 6 is used to calculate the difference from the original signal. This difference output is passed through a third coefficient unit 7, a limiter 8, and then a second force Ω calculator 9.
Vertical emphasis is applied by adding it to the original signal using . During reproduction, the values of coefficients Kp and X are determined so that the characteristics are completely opposite to those during recording, de-emphasis is performed, and S/H is improved.

Problems to be Solved by the Invention However, in the conventional configuration as described above, a delay device for vertical emphasis is required in addition to the usual delay device for dropout compensation, delay device for line noise canceller, etc. The problem is that the number of delay devices increases and the cost increases accordingly.

＼ In view of the above problems, the present invention provides dropout compensation by only using a 1H delay line.

It attempts to realize a line noise canceller, a vertical emphasis, and a 4vA capability that is a combination of a line noise canceller and a vertical de-emphasis.

Means for Solving the Problems In order to solve the above problems, the luminance signal processing circuit of the present invention includes a 1H delay device, a first coefficient multiplier that multiplies the output of the 1H delay device by Kp, and an input signal and the output of the first coefficient unit, and outputs the result to the 1H delay unit; and the output of the 1H delay unit 14 and the first coefficient. a first subtractor that takes the difference between the output of the first subtractor and the input signal; a second subtractor that takes the difference between the output of the first subtractor and the input signal; and the output of the second subtractor is multiplied by X. The output of the second coefficient multiplier and the output of the second coefficient multiplier are −M punishment;i,,I
a first switch that turns on and off the output of the limiter using a dropout compensation pulse; a second adder that adds the output of the first switch and the input signal; a second switch that is provided between a terminal and the first adder and switches between the input signal and the output of the 1H delay device using the dropout compensation pulse; and a switch @3, which is provided between the adder and the first subtracter, and is turned on and off by the dropout compensation pulse (jff L, when vertical emphasis is applied, K, = 1 and It has a coefficient of X=Xl, and when the line noise canceller is operating, K, RI0 or the third switch is off, and has a coefficient of X=X2, and functions as both vertical 1α direction de-emphasis and line noise canceller operation When the operating characteristics are combined, the transfer function of the characteristics is 1/(1+m) + mZ-' (m is a coefficient, z-1 means a 1H delay device)
It is configured to have a coefficient of

Operation The present invention has the above-described configuration, and only the 1H delay device is used to control f.
fl rectangular same direction emphasis in noise canceller,
4. Characteristics that combine mold mouth 1-way de-emphasis and line noise canceller, and dropout compensation.
It is possible to achieve two functions and configure a system fP with excellent cost performance.

Embodiment Hereinafter, a luminance signal processing circuit according to an embodiment of the present invention will be described.
This will be explained with reference to the drawings.

In FIG. 41, 11 is a 1H delay device, the output side of which is connected to a first coefficient multiplier 12 having coefficients.

The output side of the first coefficient multiplier 12 is
It is connected to the north 1 adder 14. This first adder 14 is connected to a first coefficient multiplier 1 which is supplied via a switch 18.
2 output and supplied from the input terminal 15 via the switch 16,
and the input signal to be cured, and the result is delayed by 1H'l
Output to 3111. The output side of the 1H delay device 11 is also read directly to the 21112 adder 17 of 11, and this first subtracter 17 receives the output of the 1H delay device 11 and the first adder after passing through the tiiJ switch 13. The difference between the output and the output of the first r& device 12 before the U device 14 is taken. 1st c/'
) the output side of the subtractor 17 is connected to a second subtractor 18;
This second subtractor 18 is connected to the output of the subtractor 17 of Kail,
After the switch 16 and the first addition O'A"J 14
Take the difference from the input signal just before. Second calculator 1
The output side of 8 is connected to a second coefficient multiplier 19, which has a coefficient X. The second coefficient multiplier 19 is connected to a limiter 20, which
1 to the second adder 221.

The second addition +a22 is the addition of the output of the limiter 20 that has passed through the switch 21 and the input (No. 11) after passing through the switch 16 and before the first adder 14:
l: 'i-Execute and output the result. The switch 16 is a changeover switch in which the subsequent point to the first adder 14 is selectively connected to either the contact 23 or the contact 24, and the contact 23 is temporarily read to the input terminal 15. ,
The contact 24 is connected to the output side of the 1Ha low voltage device 11.

25 is Dropout Ml! It is an input terminal for pulses and is connected to each switch 18 , 16 , 21 .

The operation of the signal processing circuit configured as described above will be explained below.

First, in the fff1 diagram, when the switch 16 is connected to the contact 28 side, the switch 13 is on, and the switch 21 is on, in the vertical emphasis mode,
Operations in eight cases, including the line noise canceller mode and a mode that combines vertical de-emphasis and line noise canceller, will be described.

First, in the case of vertical emphasis mode,
The input signal is input from the input terminal 15 in FIG. 1, passes through the switch 16 set to the contact 23 side, passes through the 1H delay section 11, and is sent to the first coefficient multiplier 12 where Kp=1. It will be done. The signal multiplied by 1 by the first coefficient p12 is sent to the first adder 14 via the switch 13, and is averaged with the input signal. On the other hand, the output of the 1H delay device 11 is also sent to the first subtracter 17, and after the level is matched by the first subtracter 17, the difference from the input signal is calculated by the second subtracter 18. This difference component is multiplied by X1 by the second coefficient multiplier 19 where X=XI, and after passing through the limiter 20,
The second adder 22 adds the signal to the original signal. This provides vertical emphasis.

Next, in the case of the line noise canceller mode, the input signal is input from the input terminal 15 in FIG.
Passes through delay device 11. The output of the Hl delay device 11 is subtracted from the input signal by a second subtracter. However, in this mode, the first coefficient multiplier 12 is set to Kp-0 or the switch 13 is turned off, and the feedback coefficient becomes 0. The output of the second subtractor 18 is the coefficient unit 1 of @2 where X=X2.
The signal is multiplied by X2 from 9f, passes through the limiter 20, and is added to the original signal at the second adder 22. This results in
The water circuit operates as a small signal comb filter, or line noise canceller.

When configuring both vertical de-emphasis and line noise canceler operation with one delay device,
The transfer function of that characteristic is 1/(1+m) −mz
' (m is a coefficient, Z-1 means a 1H delay device). This transfer function shows a characteristic that is the sum of two characteristics: vertical de-emphasis and line noise canceller characteristic. The input signal passes through the input terminal 15, the switch 16, the 1H delay device 11, and is expressed as Kp==X=m/(
1+m) is sent to the first coefficient multiplier 12. After the output of the first coefficient multiplier 12 passes through the switch 13,
9 added to the input signal in the first adder 14, and the output of the first coefficient multiplier 12 is subtracted from the output from the 1H delay device 11 by the first subtracter 17, Thereafter, the second subtracter 18 calculates the difference from the input signal. The output of the second subtracter 18 is sent to the second adder 22 after passing through the limiter 20 and the second coefficient τ subtracter 19 having the relationship of Xw-m/(1+m). and is added to the ++% signal. As a result, it is possible to achieve characteristics that combine hair: σ direction de-emphasis and line noise canceller characteristics.

If dropout occurs in the line noise canceller mode described above or when vertical 1α direction de-emphasis and line noise canceller mode are combined,
A dropout compensation pulse is manually input from the input terminal 25. This dropout compensation pulse causes switch 1
6 is switched to the contact 24 side, switch 13 is turned off,
Switch 21 is turned off. Therefore, 1H delay device 1
The information stored in 1 is added to the adder @2 via the switch 16 connected to the contact 24 and output.
Compensation is provided in case of dropout.

Effects of the Invention As described above, according to the present invention, only a 1H delay device can achieve four characteristics: vertical emphasis, line noise canceller, a combination of vertical de-emphasis and line noise canceler characteristics, and dropout compensation. The excellent effect of being able to provide functions and characteristics can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a luminance signal processing circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional luminance signal processing circuit. 11...1H delay unit, 12...first coefficient unit, 13
...Switch (third switch), 14...7A1
adder, 15...input 1 child, 16...switch (second switch), 17...first,
18... 2nd subtractor, 19... 2nd coefficient unit, 2
0...Limiter, 21...Switch (ml switch), 22...(Adder for warehouse 2).

Claims (1)

[Claims] A 1, 1H delay device, a first coefficient multiplier that multiplies the output of the 1H delay device by K_p, an input signal and the output of the first coefficient multiplier, and the result is added to the a first adder that outputs an output to a 1H delay device; a first subtracter that takes the difference between the output of the 1H delay device and the output of the first coefficient device; and an output of the first subtracter. and the input signal, a second coefficient multiplier that multiplies the output of the second subtractor by X, and a limiter that limits the amplitude of the output of the second coefficient
a first switch that turns on and off the output of the limiter using a dropout compensation pulse; a second adder that adds the output of the first switch and the input signal; a second switch that is provided between the 1H adder and the 1H delay device and switches between the input signal and the output of the 1H delay device using the dropout compensation pulse;
a third switch provided between the first coefficient multiplier, the first adder and the first subtractor and turned on and off by the dropout compensation pulse; Sometimes K_p=1 and X=X1
When operating as a line noise canceller, K_p=0 or the third switch is off, and X=X2, and when the operating characteristic combines vertical de-emphasis and line noise canceller operation, , its characteristic transfer function 1/(1+m)-mz^-^1 (m is a coefficient, z^-^1 means a 1H delay device) and the corresponding X=-m/(1+m), K_p=- A luminance signal processing circuit configured to have a coefficient X.