JPH01142940A - Microprogram controller - Google Patents

Abstract

PURPOSE:To reduce the cost of the microprogram controller and to make it compact by performing microprogram control over central processing unit by sharing a single control storage. CONSTITUTION:A clock generating circuit 15 generates operating clocks of two central processing units which are equal in frequency and different in phase. Then a selector 17 selects individual addresses in order from addresses outputted by 1st and 2nd microprogram execution control parts 12a and 12b for each of the phases of the operation clocks, and outputs them to a control storage part 11. Consequently, the microprogram control over the central processing unit is performed by sharing the single control storage and the controller is reduced in cost and made compact.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a microprogram control device used in a central processing unit, and particularly to a microprogram control device for controlling multiple central processing units in parallel. The present invention relates to a microprogram control device that performs manual operations.

(Prior Art) Conventionally, microprogram control in a CPU (central processing unit) is executed as shown in FIG. That is, when the address of the control storage unit 2 is specified by the microprogram execution control unit 1, the specified storage content, the microinstruction, is temporarily set in the microinstruction register 3, and then transferred to the arithmetic control unit 4 and Microb f' is output to the program execution control section 1. This causes w! in the arithmetic control unit 4! 4-arithmetic control is determined, and the microprogram execution control unit 1 controls the execution of the next step of the microprogram.

By the way, recently, multiple computer systems configured to perform such microprogram control on multiple CPUs in parallel have been widely used, and this allows the sharing of hardware and software resources to increase control capacity and expansion. It has been realized that the aim is to increase sex.

However, since such multiple computer systems are usually equipped with the same CPU and each CPU is equipped with a control memory section with the same memory contents, it is considered wasteful from the viewpoint of the minimum necessary functional configuration. However, it has disadvantages in terms of cost and compactness.

(Problems to be Solved by the Invention) The present invention is intended to solve the problems of conventional microprogram control devices, and performs microprogram control for multiple central processing units by sharing a single control memory. It is an object of the present invention to provide a microb 1 cogram control device that can eliminate waste in the configuration, reduce costs, and make it more compact.

[Configuration 1 of the Invention (Means for Solving the Problems) In order to achieve the above object, the present invention has the following features:
Multiple central locations]! i! In a microprogram control device that performs microprogram control on a device in parallel, a memory in which the microprograms are stored and a plurality of microprograms that each output the address of a microinstruction in the memory to be executed by each central processing unit. an execution control unit, a clock generation circuit that generates operating clocks for each of the plurality of central processing units with the same frequency and different phases; and a selector that sequentially selects individual addresses for each phase of each clock and outputs the selected addresses to the memory.

Further, in a second invention, in a microprogram III control device that performs microprogram control for a plurality of central processing units in parallel, an input/output port in which a microprogram is stored and corresponding to each of the plurality of central processing units is provided. and a plurality of microprogram execution control units that output each address of a microinstruction to be executed by each of the plurality of central processing units to the memory through a corresponding input port.

(Function) In the microprogram control device of the present invention, in the first aspect, the clock generation circuit generates operation clocks for each of the plurality of central processing units having the same frequency and different phases, and the selector generates operation clocks for each of the plurality of central processing units, and the selector generates operation clocks for each of the plurality of central processing units. Since individual addresses are sequentially selected from among the addresses output from multiple microprogram execution control units for each phase of this operating clock and output to the memory, microprogram control for multiple central processing units can be performed in a single manner. This makes it possible to share the control memory of the two devices, thereby making it possible to reduce costs and make the device more compact.

Furthermore, in the second invention, the memory in which one microphone, one cogram, is stored is configured to have input/output ports respectively corresponding to a plurality of central processing units, and the plurality of microprogram execution control units are configured to have input/output ports corresponding to each central processing unit. Since each address of the microinstruction to be executed is output to the memory through the corresponding input port, it is possible to perform microprogram control for multiple central processing units by sharing a single control memory. This makes it possible to reduce costs and make the device more compact.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 shows a microprogram system t[
1 is a block diagram for explaining the configuration of a device. The microprogram control device in the figure is one that performs microprogram control in parallel for two CPLJs provided in a multi-computer system.

In the same figure, reference numeral 11 denotes a control storage section in which a common microprogram is stored for each of the above-mentioned CPUs, 12a,
12b is a first and second microprogram execution control unit each outputting an address for specifying a microinstruction to be executed by each CPU to the control storage unit 11; 13a and 13b are each output from the control storage unit 11; The first and second microinstruction registers 14a and 14b, which temporarily hold the read microinstructions, execute the performance control of each CPU based on the microinstructions held in the respective microinstruction registers 13a and 13b. These are first and second arithmetic control units.

In addition, 15 is the operational disk A, B used by each CPU.
As shown in FIG. 2, the clocks A1B outputted from the clock generating circuit 15 have the same frequency and different phases. Further, reference numeral 16 is an FS[EL flip-flop whose set/reset state is switched at each fall of each clock A1B generated by the clock generation circuit 15, that is, this FSEL flip-flop 16 is in the set state when the clock is generated, and when the clock is generated, It is configured to enter a reset state when B occurs.

Further, 17 indicates each microprogram execution control unit 12a, 1
FSEL flip 70 from the address output from 2b
This is a selector that selects one of the addresses depending on the state of the knob 16 and outputs the selected address to the control storage section 11.

Next, the operation of this microprogram control device will be explained.

First, addresses specifying microinstructions to be executed by each CPU are entered into the selector 17 from the first and second microphone execution control units 12a and 12b, respectively.

Here, when the FSEL flip-flop 16 is set, the selector 17 selects the address input from the first microprogram execution control section 12a and outputs it to the control storage section 11. As a result, the microinstruction corresponding to the address is read from the control storage unit 11, and further set in the first microinstruction register 13a by the write clock C output from the first microprogram execution control unit 12a according to the clock A. Ru.

Further, when the FSEL flip-flop 16 is reset, the selector 17 selects the address input from the second microprogram execution control section 12b and outputs it to the control storage section 11. As a result, the microinstruction corresponding to the address is read from the control storage unit 11, and further set in the second microinstruction register 13b by the write clock D output from the second microprogram execution control unit 12b according to the clock B. Ru.

Thereafter, the microinstructions set in the microinstruction registers 13a and 13b are output to the corresponding arithmetic control units 14a and 114b according to the respective clocks A and B, and each microprogram is executed.
1 part 12a, 12bk are output, and each VJ
Each calculation control in the calculation subcontrol units 4a and 14b is executed, and each microprogram execution control unit 1
At steps 2a and 12b, execution control of the next step microprogram is started.

Thus, according to the microprogram control device of this embodiment, the single control storage section 11 is controlled by each operating clock A1B in the microprogram control operation of each CPU.
By using it for each phase, it becomes possible to perform microprogram control of two CPUs by sharing a single control storage section 11, and as a result, it is possible to eliminate wasteful configuration in a multi-computer system. , cost reduction and compactness can be achieved.

Next, other embodiments of the present invention will be described.

FIG. 3 is a block diagram for explaining the configuration of a microprogram control device according to another embodiment of the present invention.The microprogram control device in the same figure is a block diagram for explaining the configuration of a microprogram control device according to another embodiment of the present invention. Each microprogram control for the CPU is performed in parallel.

In the same figure, reference numeral 21 denotes a control storage section in which a microprogram common to the two CPUs mentioned above is stored, and this control storage FIS 21 corresponds to two address input ports (not shown) and these input ports, respectively. It is said to be a multi-port memory equipped with an output port. Further, 22a122b are first and second microprogram execution control units 23a, 2 which output addresses for specifying microinstructions to be executed by each CPU to the control storage unit 21 through corresponding input ports.
3b are first and second microinstruction registers that temporarily hold microinstructions output from each output port of the il+control storage unit 21, and 24a and 24b are held in microinstruction registers 23a and 23b, respectively. These are first and second arithmetic control units that execute arithmetic control based on microinstructions.

Next, the operation of this embodiment device will be explained.

First, an address for specifying a microinstruction to be executed by the first arithmetic operation control section 24a is output from the first microprogram execution control section 22a to the control storage section 21 via the corresponding input port. As a result, a microinstruction corresponding to the address is outputted from the control storage unit 21 from the output port corresponding to the input port into which the address was input, and is set in the first microinstruction register 23a.

Similarly, an address for specifying a microinstruction to be executed by the second arithmetic control unit 24b is output from the second microprogram execution control unit 22b to the control memory rA21 via the corresponding input port. Ru. As a result, a microinstruction corresponding to the address is outputted from the v control storage unit 21 from the output port corresponding to the input port to which the address was entered manually, and the second microinstruction register 2
Set to 3b.

The microinstructions set in the microinstruction registers 23a, 23b are output to the corresponding first and second performance II/III control units 24a, 24b, respectively, and the microprogram execution control units 22a,
22b, each arithmetic control unit 24a, 24b executes arithmetic control based on each microinstruction, and each microprogram execution control unit 22a, 22b executes arithmetic control based on each microinstruction.
At step 2b, execution control of the next step of the microprogram is started.

Thus, according to the microprogram execution control unit of this embodiment, the control storage unit 21 is a multi-port memory having two input ports and output ports respectively corresponding to these two input ports. C.P.
A single 0 control memory 2 controls the execution of microinstructions in U.
1 can be used in common, it is possible to eliminate waste in the configuration of a multiple computer system, and it is possible to reduce costs and make the system more compact.

Note that the two embodiment devices described above each perform microprogram control on two CPUs, but the present invention is not limited to this. By increasing the number of selections in the selector in the example and the number of input/output ports in the control storage unit in the following other embodiments, it is possible to perform microprogram control for three or more CPUs.

Further, the present invention can obtain similar effects even when applied to an input/output control device such as a disk control device.

Furthermore, the control storage section in the microprogram control device of the above embodiments may be ROM or RAM;
In the case of M, the microprogram only needs to be loaded once, so
It is also possible to reduce loading time.

[Effects of the Invention 1] As explained above, according to the microprogram control device of the present invention, a single control memory is shared to perform microprogram control for a plurality of central processing units, thereby reducing waste in configuration. It can be removed, reducing costs and making it more compact.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the configuration of a microprogram control device according to an embodiment of the present invention, and FIG. FIG. 3 is a block diagram for explaining the configuration of a microprogram control device according to another embodiment of the present invention, and FIG. 4 is a timing chart showing the relationship between set/reset states. FIG. 3 is a block diagram for explaining program control. 11.21... Control storage section, 12a122a... First microprogram execution control section, 12b, 22b.
...Second microprogram execution control unit, 13a, 2
3a...first microinstruction register, 13b, 23
b...Second microphone [1 instruction register, 14a, 24
a・m 1 (7) Performance 1!11111all, 14
b, 24b... Second arithmetic control unit, 15... Clock generation circuit, 16... FSEL flip 70 tube, 1
7...Selector. Applicant Toshiba Corporation Representative Patent Attorney Sasa Suyama −・

Claims (2)

[Claims] (1) In a microprogram control device that performs microprogram control for multiple central processing units in parallel, the memory in which the microprogram is stored and the address of the microinstruction in the memory to be executed by each central processing unit a plurality of microprogram execution control units that each output a clock, a clock generation circuit that generates operation clocks for each of the plurality of central processing units having the same frequency and different phases; A microprogram control device comprising: a selector that sequentially selects individual addresses from each address for each phase of each clock generated by the clock generation circuit and outputs the selected addresses to the memory. (2) a microprogram control device that performs microprogram control for a plurality of central processing units in parallel; A microprogram control system comprising: a plurality of microprogram execution control units that output each address of a microinstruction to be executed by each of the plurality of central processing units to the memory via the corresponding input port. Device.