JPH01143420A - Frequency synthesizer - Google Patents
Frequency synthesizerInfo
- Publication number
- JPH01143420A JPH01143420A JP62299731A JP29973187A JPH01143420A JP H01143420 A JPH01143420 A JP H01143420A JP 62299731 A JP62299731 A JP 62299731A JP 29973187 A JP29973187 A JP 29973187A JP H01143420 A JPH01143420 A JP H01143420A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- phase
- voltage
- frequency
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000035945 sensitivity Effects 0.000 claims abstract description 19
- 238000001514 detection method Methods 0.000 claims abstract description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 3
- 238000013016 damping Methods 0.000 description 2
- 241000272814 Anser sp. Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は送信或いは受信周波数変換器の局発信号として
使用される周波数シンセサイザに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency synthesizer used as a local oscillator signal for a transmitting or receiving frequency converter.
従来、この種の用途に用いられる周波数シンセサイザの
一例を第２図に示す。この周波数シンセサイザでは、基
本周波数発生器ｌの出力信号は分周器２により予め設定
された値Ｒで分周され、位相比較器３に供給される。一
方、電圧制御発振器５の出力信号の一部は、ディジタル
スイッチ７の制御信号により分周比Ｎが設定される可変
分周器６に供給され、Ｎ分周された信号は位相比較器３
に供給され、ここで前述の基準周波数信号と位相比較さ
れる。位相比較器３の出力の位相誤差信号はループフィ
ルタ４を介して電圧制御発振器５の周波数制御端子へ供
給される。An example of a frequency synthesizer conventionally used for this type of application is shown in FIG. In this frequency synthesizer, the output signal of the fundamental frequency generator l is frequency-divided by a preset value R by a frequency divider 2 and supplied to a phase comparator 3. On the other hand, a part of the output signal of the voltage controlled oscillator 5 is supplied to a variable frequency divider 6 whose frequency division ratio N is set by the control signal of the digital switch 7, and the N-divided signal is supplied to the phase comparator 3.
, where the phase is compared with the reference frequency signal mentioned above. The phase error signal output from the phase comparator 3 is supplied to a frequency control terminal of a voltage controlled oscillator 5 via a loop filter 4.
このようにして位相同期ループが構成されて、位相誤差
が最小となるようにループが動作する結果、電圧制御発
振器５の出力信号周波数は基準周波数信号の周波数安定
度と同等に保持される。A phase-locked loop is configured in this way, and as a result of the loop operating so that the phase error is minimized, the output signal frequency of the voltage controlled oscillator 5 is maintained at the same frequency stability as the reference frequency signal.
この時の出力周波数並びにループフィルタとして第３図
に示す演算増幅器ＯＰ、コンデンサＣ２抵抗Ｒ，、Ｒ２
で構成したアクティブフィルタを用いた時のループの自
然周波数ω７．ループのダンピングファクタζが次式で
表されることは周知のとおりである。At this time, the output frequency and loop filter are as shown in Fig. 3: operational amplifier OP, capacitor C2, resistor R,, R2.
The natural frequency of the loop when using an active filter configured with ω7. It is well known that the damping factor ζ of the loop is expressed by the following equation.
ｆ ｖｃｏ ＝Ｎ ｆ＊ ／Ｒ
ω１ ＝ （Ｋ φ Ｋ ｖ ／ＮＴ、 ） 鵞／２
ぐ＝Ｔ２ω、ｌ／２
ここで、
ｒｖｃ。＝電圧制御発振器の出力周波数ｆＲ＝基準信号
の周波数
にφ＝位相比較器の検波感度（Ｖ／ｒａｄ）Ｋｖ＝電圧
制御発振器の変調感度（ｒａｄ／Ｖ）Ｔ ＋ ＝ ＣＲ
Ｉ
Ｔｚ＝ＣＲｚ
〔発明が解決しようとする問題点〕
上述した周波数シンセサイザを広帯域にて動作させる場
合には、可変分周器６の分周比Ｎを大きく変化させるよ
うにすればよい。しかしながら、周波数範囲の拡大に伴
って、電圧制御発振器５の変調感度Ｋｖの変化は大きく
なる。このため、これらの分周比Ｎ、変調感度Ｋｖに依
存しているループの自然周波数、ダンピングファクタが
変化され、出力信号の位相雑音や位相同期ループの過度
応答特性が大きく変化するという問題がある。f vco =N f* /R ω1 = (K φ K v /NT, ) Goose/2
gu=T2ω, l/2 where, rvc. = Output frequency of voltage controlled oscillator fR = Frequency of reference signal φ = Detection sensitivity of phase comparator (V/rad) Kv = Modulation sensitivity of voltage controlled oscillator (rad/V) T + = CR
I Tz=CRz [Problems to be Solved by the Invention] When the above-described frequency synthesizer is operated in a wide band, the frequency division ratio N of the variable frequency divider 6 may be greatly changed. However, as the frequency range expands, the change in modulation sensitivity Kv of the voltage controlled oscillator 5 increases. Therefore, the natural frequency and damping factor of the loop, which depend on the frequency division ratio N and modulation sensitivity Kv, are changed, causing a problem that the phase noise of the output signal and the transient response characteristics of the phase-locked loop change significantly. .
本発明は、広帯域にわたった安定な動作が可能な周波数
シンセサイザを提供することを目的としている。An object of the present invention is to provide a frequency synthesizer capable of stable operation over a wide band.
本発明の周波数シンセサイザは、電圧制御発振器の出力
信号を可変分周器で分周した信号と基準信号とを位相比
較する位相比較器を供給電圧に対応した検波感度を有す
る構成とし、これに可変分周器の分周比設定用の制御信
号を所定の相関で電圧に変換して位相比較器に供給する
手段を設けた構成としている。The frequency synthesizer of the present invention has a phase comparator that compares the phase of a signal obtained by dividing the output signal of a voltage controlled oscillator with a variable frequency divider and a reference signal, and has a detection sensitivity corresponding to the supply voltage. The configuration includes means for converting a control signal for setting the frequency division ratio of the frequency divider into a voltage with a predetermined correlation and supplying the voltage to the phase comparator.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
基準周波数信号発生器１の出力信号は、分周器２により
分周比Ｒで分周されて位相比較器３に供給される。また
、電圧制御発振器５の出力信号の一部は、ディジタルス
イッチ７からの制御信号により分周比Ｎが設定される可
変分周器６により分周されて前記位相比較器３に供給さ
れる。The output signal of the reference frequency signal generator 1 is frequency-divided by a frequency division ratio R by a frequency divider 2 and supplied to a phase comparator 3. Further, a part of the output signal of the voltage controlled oscillator 5 is frequency-divided by a variable frequency divider 6 whose frequency division ratio N is set by a control signal from a digital switch 7, and then supplied to the phase comparator 3.
前記位相比較器３はこの２つの信号の位相差を検出し、
位相誤差信号をループフィルタ４を介して電圧制御発振
器５の周波数制御入力端子に帰還する。これにより位相
同期ループが構成され、電圧制御発振器５の出力周波数
は基準周波数信号の周波数安定度と同一に保持される。The phase comparator 3 detects the phase difference between these two signals,
The phase error signal is fed back to the frequency control input terminal of the voltage controlled oscillator 5 via the loop filter 4. This constitutes a phase-locked loop, and the output frequency of the voltage controlled oscillator 5 is maintained at the same frequency stability as the reference frequency signal.
ここで、前記位相比較器３は、供給される電圧に比例し
た検波感度を有するように構成されている。例えば、チ
ャージポンプにＣＭＯ３を使用したものがあり、これは
電源電圧に比例する感度を有している。Here, the phase comparator 3 is configured to have detection sensitivity proportional to the supplied voltage. For example, there is a charge pump using CMO3, which has a sensitivity proportional to the power supply voltage.
一方、前記可変分周器６の分周比を変化させるディジタ
ルスイッチ７の制御信号は、データ変換器８によりデー
タ変換され、Ｄ／Ａ変換器９に供給される。そして、こ
のＤ／Ａ変換器９の出力直流電圧信号は、ボルテージフ
ォロア１０を経て前記位相比較器３の電源端子に供給さ
れる。したがって、この位相比較器３に供給される電圧
は、前記ディジタルスイッチ７の制御信号に対してデー
タ変換器８の設定内容に応じて所定の相関を有すること
になる。On the other hand, a control signal for the digital switch 7 that changes the frequency division ratio of the variable frequency divider 6 is converted into data by a data converter 8 and supplied to a D/A converter 9. The output DC voltage signal of this D/A converter 9 is supplied to the power supply terminal of the phase comparator 3 via a voltage follower 10. Therefore, the voltage supplied to the phase comparator 3 has a predetermined correlation with the control signal of the digital switch 7 according to the settings of the data converter 8.
この周波数シンセサイザによれば、ディジタルスイッチ
７の制御信号により可変分周器６の分周比を変更すると
、この制御信号と相関を有する電圧が位相比較器３に供
給され、その検波感度が変化されることになる。したが
って、データ変換器８における変換内容を、出力周波数
に対する電圧制御発振器の変調感度の変化と分周比Ｎの
変化とに対応して予め設定しておけば、分周比に応じて
電圧制御発振器の変調感度を適切に制御でき、位相同期
ループの特性を広帯域にわたって殆ど一定にすることが
できる。これにより、出力信号の位相雑音を小さくする
ことができ、また過度応答特性を最適にする等、広帯域
にわたって安定な動作が得られる。According to this frequency synthesizer, when the frequency division ratio of the variable frequency divider 6 is changed by the control signal of the digital switch 7, a voltage having a correlation with this control signal is supplied to the phase comparator 3, and its detection sensitivity is changed. That will happen. Therefore, if the conversion contents in the data converter 8 are set in advance in accordance with changes in the modulation sensitivity of the voltage controlled oscillator with respect to the output frequency and changes in the frequency division ratio N, the voltage controlled oscillator The modulation sensitivity of the phase-locked loop can be appropriately controlled, and the characteristics of the phase-locked loop can be made almost constant over a wide band. As a result, the phase noise of the output signal can be reduced, transient response characteristics can be optimized, and stable operation can be obtained over a wide band.
なお、周波数設定間隔は分周比Ｎと変調感度の変化の度
合に応じて適宜設定しておけばよい。Note that the frequency setting interval may be appropriately set according to the frequency division ratio N and the degree of change in modulation sensitivity.
〔発明の効果］
以上説明したように本発明は、位相同期ループにおける
位相比較器を供給電圧に対応した検波感度を有する構成
とし、これに可変分周器の制御信号を所定の相関で電圧
に変換して位相比較器に供給する手段を設けているので
、分周比に応じて電圧制御発振器の変調感度を適切に設
定でき、位相同期ループの特性を広帯域に渡って最適な
値に設定して出力信号の位相雑音を小さくし、かつ過度
応答特性を最適化する等、広帯域に渡って安定な動作を
する周波数シンセサイザが実現できる。[Effects of the Invention] As explained above, the present invention configures the phase comparator in the phase-locked loop to have a detection sensitivity corresponding to the supplied voltage, and applies the control signal of the variable frequency divider to the voltage with a predetermined correlation. Since a means is provided to convert the signal and supply it to the phase comparator, the modulation sensitivity of the voltage controlled oscillator can be appropriately set according to the frequency division ratio, and the characteristics of the phase-locked loop can be set to the optimum value over a wide band. It is possible to realize a frequency synthesizer that operates stably over a wide band by reducing the phase noise of the output signal and optimizing the transient response characteristics.
第１図は本発明の周波数シンセサイザの一実施例のブロ
ック図、第２図は従来の周波数シンセサイザのブロック
図、第３図は位相同期ループを構成するループフィルタ
の一例を示す回路図である。
１・・・基準周波数信号発生器、２・・・分周器、３・
・・位相比較器、４・・・ループフィルタ、５・・・電
圧制御発振器、６・・・可変分周器、７・・・ディジタ
ルスイッチ、８・・・データ変換器、９・・・Ｄ／Ａ変
換器、１０・・・ボ第１図FIG. 1 is a block diagram of an embodiment of the frequency synthesizer of the present invention, FIG. 2 is a block diagram of a conventional frequency synthesizer, and FIG. 3 is a circuit diagram showing an example of a loop filter constituting a phase-locked loop. 1... Reference frequency signal generator, 2... Frequency divider, 3.
... Phase comparator, 4... Loop filter, 5... Voltage controlled oscillator, 6... Variable frequency divider, 7... Digital switch, 8... Data converter, 9... D /A converter, 10... Figure 1
Claims (1)
た信号と基準信号とを位相比較器で位相比較し、その位
相誤差信号をループフィルタを介して前記電圧制御発振
器に負帰還する位相同期ループで構成された周波数シン
セサイザにおいて、前記位相比較器は供給電圧に対応し
た検波感度を有する構成とし、これに前記可変分周器の
分周比設定用の制御信号を所定の相関で電圧に変換して
前記位相比較器に供給する手段を設けたことを特徴とす
る周波数シンセサイザ。(1) A phase comparator compares the phase of a signal obtained by dividing the output signal of the voltage controlled oscillator using a variable frequency divider and a reference signal, and negatively feeds back the phase error signal to the voltage controlled oscillator via a loop filter. In a frequency synthesizer configured with a phase-locked loop, the phase comparator has a detection sensitivity corresponding to the supply voltage, and a control signal for setting the division ratio of the variable frequency divider is applied to the voltage with a predetermined correlation. A frequency synthesizer comprising means for converting the signal into a signal and supplying the signal to the phase comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62299731A JPH01143420A (en) | 1987-11-30 | 1987-11-30 | Frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62299731A JPH01143420A (en) | 1987-11-30 | 1987-11-30 | Frequency synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01143420A true JPH01143420A (en) | 1989-06-06 |
Family
ID=17876282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62299731A Pending JPH01143420A (en) | 1987-11-30 | 1987-11-30 | Frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01143420A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788418A (en) * | 2016-11-15 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | A kind of signal source outside FM circuit and method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848145B2 (en) * | 1980-05-20 | 1983-10-26 | 雪印乳業株式会社 | Method for producing cheese products with filamentous structure |
-
1987
- 1987-11-30 JP JP62299731A patent/JPH01143420A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848145B2 (en) * | 1980-05-20 | 1983-10-26 | 雪印乳業株式会社 | Method for producing cheese products with filamentous structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788418A (en) * | 2016-11-15 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | A kind of signal source outside FM circuit and method |
| CN106788418B (en) * | 2016-11-15 | 2020-06-09 | 中国电子科技集团公司第四十一研究所 | A signal source external frequency modulation circuit and method |
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