JPH01145191U - - Google Patents
Info
- Publication number
- JPH01145191U JPH01145191U JP4025388U JP4025388U JPH01145191U JP H01145191 U JPH01145191 U JP H01145191U JP 4025388 U JP4025388 U JP 4025388U JP 4025388 U JP4025388 U JP 4025388U JP H01145191 U JPH01145191 U JP H01145191U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- superintegrated
- assigned
- emulation
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
- Tests Of Electronic Circuits (AREA)
Description
第１図は、本考案のエミユレータ接続用の延長
基板の平面図、第２図は、スーパーインテグレー
シヨンサーキツト基板（ＳＩＩＣ基板）の平面図
である。
１……延長基板、２……ＳＩＩＣソケツト（ス
ーパーインテグレーシヨンサーキツトソケツト）
、３……伝送線、４……伝送線、５……ＳＩＩＣ
基板（スーパーインテグレーシヨンサーキツト基
板）、６……ＳＩＩＣ（スーパーインテグレーシ
ヨンサーキツト）、７……制御線、８……信号線
、Ｐ１，Ｐ２……延長基板のコネクタ、Ｐ３，Ｐ
４……ＳＩＩＣ基板のコネクタ、ＰＪ１……回路
切替用プラグ。
FIG. 1 is a plan view of an extension board for connecting an emulator according to the present invention, and FIG. 2 is a plan view of a super integration circuit board (SIIC board). 1...Extension board, 2...SIIC socket (super integration circuit socket)
, 3...transmission line, 4...transmission line, 5...SIIC
Board (super integration circuit board), 6...SIIC (super integration circuit), 7...control line, 8...signal line, P1, P2...extension board connector, P3, P
4... SIIC board connector, PJ1... circuit switching plug.
Claims (1)
まれるプロセツサの外部エミユレーシヨンに必要
な信号線をスーパーインテグレーシヨン化された
回路のパツケージの足に割り付けるとともに、前
記プロセツサがバスを放棄する制御線を前記スー
パーインテグレーシヨン化された回路のパツケー
ジの他の足に割り付け、前記信号線をエミユレー
タと接続するための接続子に接続し、かつ前記制
御線をエミユレーシヨン動作のための切替え操作
子に接続したことを特徴とする延長基板。 The signal lines necessary for external emulation of the processor included in the superintegrated circuit are assigned to the legs of the package of the superintegrated circuit, and the control lines on which the processor relinquishes the bus are assigned to the superintegrated circuit. the signal line is connected to a connector for connecting to an emulator, and the control line is connected to a switching operator for emulation operation. substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4025388U JPH01145191U (en) | 1988-03-29 | 1988-03-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4025388U JPH01145191U (en) | 1988-03-29 | 1988-03-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01145191U true JPH01145191U (en) | 1989-10-05 |
Family
ID=31266727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4025388U Pending JPH01145191U (en) | 1988-03-29 | 1988-03-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01145191U (en) |
-
1988
- 1988-03-29 JP JP4025388U patent/JPH01145191U/ja active Pending