JPH01149592A - Line controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line control device, and particularly to a line control device that transfers a plurality of status display signals and control signals for each subscriber.

[Conventional technology]

Conventional line control equipment is based on the "
D70 type automatic exchange ■Hardware (1)'' No. 154
As described in pages 155, 169-172, and 176-178, K includes a memory that stores a plurality of status display signals for each subscriber that are constantly sent out from the subscriber line termination circuit, and a memory that constantly transfers them to the subscriber line termination circuit. The memory for storing a plurality of control signals for each subscriber was comprised of different memory units.

[Problem that the invention seeks to solve]

When there are many subscribers, the capacities of the memory for storing status display signals and the memory for storing control signals need to be made proportional to the number of subscribers. On the other hand, when an IC memory is used as the memory, the minimum capacity is generally determined by the type of IC memory. Therefore, when the number of subscribers is small relative to the memory capacity, the conventional line control device
There is a problem that it is uneconomical because two memos with low usage rate are used.

An object of the present invention is to provide an economical line control device even when the number of subscribers is small.

[Ninth way to solve the problem]

The above purpose is to provide an interface section that interfaces with the upper processing device, a memory section that stores status display signals and control signals, and a memory section that controls the memory section using instructions from the upper processing device that are sent via the interface section. , and control that autonomously writes the status display signal constantly sent from the subscriber line termination circuit into the memory section, and autonomously always reads out the control signal stored in the memory section and transfers it to the subscriber line termination circuit. a control unit that controls the direction of the status display signal or control signal read from the memory unit under control from the control unit, and a direction control unit that performs direction control of the status display signal or control signal written to the friend memory unit. This is achieved by providing the line control device with the following.

[Effect]

The above memory section is configured to store both status display signals and control signals, so if the number of subscribers is small, one memory section can be shared without providing two memories, making it economical. It becomes possible to obtain a line control device.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, the upper processing device 2 is a line control bag gL.
Control 1. Further, the line control device 1 always sends a control signal 12 to the subscriber line termination circuit 5, and the subscriber line termination circuit 5 always sends a status display signal 11 to the line control device 1. The line control device 1 includes an interface section 5 having an interface with the host processing device 2, a memory section 4 that stores status display signals and control signals, and a control section 6, which will be described later, to write and read data into the memory section 4. The direction control unit 7 and the memory unit 4 control the direction of
The control section 6 is configured to perform control.

Next, the operation of the line control device 1 will be explained using FIG. 2. At time t, the control unit 6 performs the next autonomous process regardless of the control of the host processing device 2.

The direction control section 7 is controlled to send the status display signal 11 sent from the subscriber line termination circuit 3 to the memory section 4 as At--memory data 8 A.

It also controls the memory unit 4 to write the memory data 8 A. As described above, the status display signal 110A is stored in the memory section 4. Next, at time t2, the control unit 6 performs all of the following autonomous processing. Memory data 80B already stored in memory unit 4? Controls reading. It also controls the direction control unit 7 to send the memory data 8 as the Bi control signal 120B to the joining @line termination circuit 5. As described above, the control signal 12 B is sent to the subscriber termination circuit 3.

Next, at time t, the control unit 6 performs the following processing under the control of the higher-level processing device @2. The direction control unit 7 is controlled to send the C of the control unit 910 sent from the host processing device 2 to the memory unit 4 as the C of the memory data 8. It also controls the memory unit 4 to write all the memory data 80C. As described above, C of the control signal 10 is stored in the memory section 4. Also at time t4, the control unit 6 performs the following processing under the control of the host processing device 2.

The memory section 4 is controlled to read out the memory data 8 D already stored therein. Control is performed on the friendly direction control unit 7 to send the D of the memory data 8 as the D of the status display signal 9 to the host processing device 2 via the interface unit 5. As a result of the above, D with status table distrust +9 is sent to the higher-level processing device fi12. Thereafter, the line control device 1 goes from time t to t4 and repeats the same processing as the next processing. In this manner, the line control device 1 stores the status display signal 11 constantly sent from the subscriber line termination circuit 3 in the memory section 4, and reads out the control signal 12't- from the memory section 4 from the subscriber line termination circuit 3. Always send to. Also, under the control of the higher-level processing device 20, the status display signal 9 stored in the memory section 4 is read out and sent to the higher-level processing device 2. Further, the control signal 10 sent from the host processing device 2 is stored in the memory section 4. Note that the state table prediction t written in the memory section 4 by the autonomous processing of the control section 6 is read out from the memory section 4 under the control of the higher-level processing device 2 of the control section 6. In addition, the control unit 6
The ratio control signal written in the memory section 4 under the control of the higher-level processing device is read out from the memory section 4 under the autonomous processing of the control section 6.

〔Effect of the invention〕

As explained above, according to the present invention, the memory for storing status display signals and the memo for storing control signals can be shared, so even in a case where the number of subscribers is small, the memory can be used economically. There is an effect that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a line control device according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the line control device shown in FIG. 1...Line control device, 2...Upper processing device, 3...
- Subscriber line termination circuit, 4... memory section, 5. ...Interface section, 6...Control section, 7...Direction control section,
8...Memory data, 9,11...Status display signal,
10.12...Control signal.

Claims (1)

[Claims] 1. A plurality of status display signals for each subscriber, which are constantly sent out from the subscriber line termination circuit on the exchange side, are transferred to the upper processing device according to a command from the upper processing device; A line control device that constantly transfers a plurality of control signals to the subscriber line termination circuit, an interface section having an interface with the higher-level processing device, a memory section that stores the status display signal and the control signal;
controlling the memory unit according to commands from the host processing unit sent via the interface unit, and autonomously writing the status display signal constantly sent from the subscriber termination circuit into the memory unit; and a control unit that autonomously always reads out the control signal stored in the memory unit and performs control to transfer it to the subscriber termination circuit, and the state read out from the memory unit under control from the control unit. Connecting the display signal and the control signal to the interface section and the subscriber line termination circuit, respectively, and selecting either the status display signal from the subscriber line termination circuit or the control signal from the interface section and storing the signal in the memory. 1. A line control device comprising: a direction control section connected to a direction control section.