JPH01150921A - Clk switching circuit - Google Patents

Abstract

PURPOSE:To switch two types of clock signals CLK with different phases and frequencies without generating glitch and waveform abnormality by providing a means to detect the phase of a clock signals, and to confirm that the clock signal becomes at a low level when the clock signal is switched. CONSTITUTION:When a Q output of a flip flop FF2 becomes at 1, an AND 8 gate is turned on, a CLKA becomes enable, further, the CLKA passes through an OR 10, and is produced as an output 17. Next, when a switching signal becomes at 0, the Q output of an FF3 becomes at 1 at the fall point of the CLKA, the Q output of an FF1 is at 0, the Q output of an FF4 is at 1 at the falling point of a CLKB, and the Q output of the FF2 is at 0 at the next falling point of the CLKA. Consequently, since the Q output of the FF2 is at 0 at the AND 8, the gate is turned off, and when the level of the CLKA is completely changed from a High 1 to a Low 0, the gate is switched. For this the CLKA is switched without being cut off in the middle or generating the glitch.

Description

Detailed Description of the Invention Technical Field The present invention provides two clock signals (hereinafter abbreviated as CLK) having different phases and periods on a large-scale integrated circuit (hereinafter referred to as LSI).
The present invention relates to a CLK switching circuit that inputs an input to one input terminal of a CLK (hereinafter referred to as "CLK switching circuit"), and particularly relates to a CLK switching circuit that can switch between two CLKs without waveform abnormalities such as glitches.

Conventional technology Hard disk drive/L called flexible disk drive disk controller (HFDC)
At SI, we refer to flexible disk drives (hereinafter referred to as FDD).
(hereinafter abbreviated as HDD) and a hard disk drive (hereinafter abbreviated as HDD) can be driven by one LSI.

In this case, the clock signal (hereinafter C
Since the CLK used to drive the HDD is different from the CLK used to drive the HDD, it is necessary to input a CLK suitable for each device.

A conventional CLK switching circuit includes AND gates 41, 42, an OR gate 44, and an inverter 43, as shown in FIG.
), a switching signal was used.

In this case, if the switching signal is '1', the AND gate 4
1, CLA is output as an output (51), and CLKA is further output as an output (53) via an OR gate 44. Also, if the switching signal is 11011, the output (
CLKB is output as 53).

However, in this method, since the CLK and the switching signal are not synchronized, the pulse width may be narrower than the original waveform, or there may be glitches, as shown by the dotted lines in each output (51) to (53) shown in Figure 5. may occur, L
There was a problem in that it had an adverse effect on SI.

Purpose The purpose of the present invention is to improve such problems and to input two CLKs with different phases and periods to the input terminal of one LSI, thereby preventing glitches from occurring when switching CLKs. Another object of the present invention is to provide a CLK switching circuit that prevents a high-level pulse width from differing from the original waveform.

Configuration In order to achieve the above object, the CLK switching circuit of the present invention has the following features:
Two types of CL with different one phase and period depending on the switching signal
The CLK switching circuit that switches and outputs the CLK is equipped with a means (flip-flop) to detect the phase of the CLK and confirm that the CLK has become low level, and when switching the CLK, the CLK is The feature is that glitches are eliminated and the pulse width of the high level is secured by switching after confirming that the low level has passed and the high level period has ended.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a CLK switching circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of a CLK switching circuit according to an embodiment of the present invention, and FIG. 3 is a disk control diagram according to an embodiment of the present invention. It is a block diagram of a device.

As shown in FIG. 3, the disk control device of this embodiment has an HF
DC31, CLK switching circuit 32. Driver/Receiver 3
3.34. Variable frequency oscillator (hereinafter abbreviated as VFO) 35 for FDD, VFO 3 for HDD
6, an FDD 37, and an HDD 38.

Also, the CLK of the FDD 37 is connected via the CLK switching circuit 32.
and CLK of HDD38 in one LSI (HFDC31
), the HFDC 31 can drive the FDD 37 and the HDD 38.

As shown in FIG.
7, AND gates (AND) 8, 9, and OR gate (OR) 10; when the switching signal is "1'', CLKA is selected; when it is "0", CLK is selected.
Select B.

Regarding the operation of the CLK switching circuit 32, as shown in FIG. 2, when the reset signal (R8T) is input (RST=
O), all FFs are reset, AND8.9 is gated off, CLKA and CLKB are output (17)
is not output to .

Also, after R3T is released (R3T=1), the switching signal is
When l u is reached, the falling point a of CLKB in FFI
The Q output becomes 1".

In this way, when the Q output of FFI becomes "1", next, at point b, the Q output of FF2 becomes "1" due to the fall of CLKA.
becomes.

At this point, the levels of CLKA and CLKB are Low (
0) is detected, and preparations for CLK switching are completed.

Furthermore, when the Q output of FF2 becomes "1", AND8 is gated on and CLKA is enabled, and further, CLKA passes through 0R10.

It is output as output (17). In other words, in period I, C
LKA is output.

Next, when the switching signal becomes "0", the Q of FF3 at point e.
The output becomes 1'1", and the Q output of FFI becomes "O" at point C.
”, the Q output of FF4 is 41171, and at point d, FF
The Q output of 2 becomes #l Ojj.

Therefore, in AND8, since the Q output of FF2 is O, the gate is turned off, and the level of CLKA becomes completely High.
It is switched when it changes from (1) to LOW (0). Therefore, CLKA can be switched without being cut off midway or without glitches occurring.

Also, since the Q output of FF4 became at 1 u, A
The gate of ND9 is enabled, and in period ■, CLK
B is output as output (17).

Next, when the switching signal becomes "1" again, FF3 at point f
The Q output of FF1 is "1"' and the Q output of FF4 is '0' at point g. At this point, AND9 is gated off and the output of CLKB is stopped.

Furthermore, at point h, the Q output of FF2 becomes El 1 jl, AND8 turns on from goo1 to on, and the output of CLKA is ready.

By remanipulating these operations, CLKA and C
LKB is output with a normal waveform without glitches or pulse width abnormalities.

Effects According to the present invention, two types of CL with different phases and periods
Since K can be switched without glitches or waveform abnormalities, it is possible to improve the reliability of the device.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a CLK switching circuit in an embodiment of the present invention, FIG. 2 is a timing chart of a CLK switching circuit in an embodiment of the present invention, and FIG. 3 is a diagram of a HFDC device in an embodiment of the present invention. FIG. 4 is a block diagram of a conventional CLK switching circuit, and FIG. 5 is a timing chart of the conventional CLK switching circuit. 1~4: Flip-flop (FF), 5~7°43:
Inverter, 8, 9, 41, 42: AND gate (AN
D), 10,44 Niorgate (OR). 31 hard disk drive/flexible disk drive disk controller (HFDC), 32
: CLK switching circuit, 33, 34: Driver/receiver, 35: VF0 for FDD, 36: VF0, 3 for HDD
7: Flexible disk drive (FDD), 38
hard disk drive (HDD), (11) ~ (
17), (51) to (53): Output, CLK, CLK
A, CLKB: Clock signal. R3T: Reset signal. Figure 3

Claims (1)

[Claims] 1. Two types of clock signals with different phases and periods,
The CLK switching circuit that switches and outputs the clock signal based on the switching signal is characterized by comprising means for detecting the phase of the clock signal and confirming that the clock signal has become low level when switching the clock signal. C.L.
K switching circuit.