JPH01154392A - Memory circuit - Google Patents

Abstract

PURPOSE:To remarkably shorten a memory initial value setting time by providing an access device for simultaneously making access to plural memory cells. CONSTITUTION:At the time of reading, a value applied to a data input terminal 9 is written through a circuit 3 to only the cell of an array 6 the contents of which of the memory cell array 6 designated by an address signal are designated by a data output terminal 70 through the column input and output circuit 3. Then, when an input signal 80 is '1', signals 20-1-20-m and signals 50-1-50-n completely go to '1' irrespective of the value of the address signal 70. Accordingly, at the time of executing a writing operation at this time, the value applied to the data input terminal 9 is written in all the memory cells in the array 6 to write the initial values of all the cells by one writing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to memory circuits, and more particularly to semiconductor memory circuits.

BACKGROUND ART A conventional memory circuit of this type encodes an input access address signal using a row decoder and a column decoder, respectively, and supplies each decoded output signal to a memory cell array. can be accessed selectively.

In such a memory circuit, the specification of a memory cell is limited to any one specified by an address.
When initializing the entire memory cell array, it is necessary to write initial values to all addresses, which has the disadvantage of requiring a large amount of time. Particularly in recent years, where the capacity of semiconductor memories has increased significantly, the time required to initialize the memory has become increasingly large.

11. An object of the present invention is to provide a memory circuit that can shorten the time required for memory initialization.

A memory circuit according to the present invention has an access means that can access all memory cells of a memory cell array at once.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

The figure is a block diagram of one embodiment of the present invention. The address signal @70 input to the address input terminal 7 is input to the column decoder 1 and row decoder 4. The output signals 10-1 to 10-1 of the column decoder 1 are ORed with the input signal 80 input to the input terminal 8 by the first OR circuit 2, and output as signals 20-1 to 20-1. and is connected to the column input/output circuit 3.

Both the data input terminal 9 and the data output terminal 10 are connected to the column input/output circuit 3, and data is read and written to and from the memory cell array 6 via signals 30-1 to 30-m and the column input/output circuit 3, respectively. be exposed. Low decoder 4
The output signals 40-1 to 40-n are ORed with the input signal 80 and the second OR circuit 5, respectively, and the output signals 50-1 to 50 are
-n and connected to the memory array 6.

To explain the operation of the memory circuit of the present invention, first, when the input signal 80 is logic "0", the address signal 70 is decoded by the column decoder 1 and the row decoder 4,
The output signals 10-1 to 10-+e and 40-1 to 40-n are directly converted to the signals 20-1 to 20-ya and the signals 50-1 to 50-1.
50-n. Therefore, when reading, the contents of the only cell in the memory cell array 6 specified by the address signal 70 is output to the data output terminal 10 via the column input/output circuit 3, and when reading, the contents of the only cell in the memory cell array 6 specified by the address signal 70 are output to the data output terminal 10, and when reading is performed, the contents of the only cell in the memory cell array 6 specified by the address signal 70 are output to the data output terminal 10.
The value applied to the data input terminal 9 is written into the only cell in the memory cell array 6 designated by 0 via the column input/output circuit 3. This operation is the same as a conventional memory circuit.

Next, when the input signal 80 is logic "1", the signal 201
.about.20-n+ and signals 50-1 to 50-11 are all logic 111 I+ regardless of the value of address signal 70. Therefore, if a write operation is performed at this time, the value given to the data input terminal 9 will be written to all memory cells in the memory cell array 6, and the initial value of all cells will be written in one write operation. It is possible to do this.

Effects of the Invention As described above, according to the present invention, all the memory cells in the memory cell array are accessed at once by one access operation, so all the memory cells can be accessed by simply one accumulation operation. It is possible to set the initial value using the method, which has the effect of significantly shortening the time required to set the memory initial value.

[Brief explanation of the drawing]

The figure is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 1...Column decoder 2.5...OR circuit 4...Low decoder 6...Memory cell array

Claims (1)

[Claims] 1. A memory circuit comprising a plurality of memory cells, characterized in that the memory circuit is provided with access means that can access all of the memory cells at once.