JPH01155395A - Graphic display - Google Patents

Abstract

PURPOSE: To obtain the graphic display device which is increased in drawing speed by providing a means for drawing a pattern in a frame memory consisting of plural dots in access units of the frame memory by using a pattern register. CONSTITUTION: A CPU specifies a drawing specified pattern 9 consisting of 8× 8 dots for the drawing of a graphic character, the drawing direction of the pattern, and the head dot to be drawn. The specification of the drawing direction consists of a pattern expansion instruction 14 and a drawing direction specification part 15, which consists of, for example, three bits, so that one of eight directions is specified at 45 deg. intervals. Data of the drawing direction specification part 15 whose drawing direction is specified are stored in a drawing direction selecting circuit 4. Then data in the drawing direction selecting circuit 4 are outputted to the pattern register 1 thorugh a pattern expansion readout control circuit 2. Consequently, the drawing speed of the graphic display device is made fast.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to graphic display devices.

[Conventional technology]

Conventionally, in graphic display devices, when drawing graphic characters, a drawing pattern specified by a CPU is first stored in a storage device called a pattern RAM, and then the CPU develops the pattern into a frame memory. When specified, drawing of the pattern is executed.

The drawing method at this time is from the 9th dot 1-, which was specified as the starting point, to the Mth in the specified direction.

This method calculates where in the frame memory the specified dot should be drawn, and then executes the process.

At this time, since there are multiple dots whose contents are not directly specified by the drawing pattern in the specified area on the frame memory, C
In accordance with the PU designation, processing is performed to fill in appropriate patterns using arithmetic processing based on old information.

Such execution will be explained using FIGS. 2(a), (b), and (c). This figure shows a case in which the specific pattern shown in FIG. 3(a) is expanded into the pattern shown in FIG. 14(b).

First, the pattern shown in FIG. 2(a) specified by the CPU is stored in the pattern RAM as is.

The pattern is drawn to the frame memory based on the pattern stored in the pattern RAM.
When developing a pattern in the direction shown in FIG. 2B, there are the same number of dots to be interpolated as the original pattern in addition to the original pattern. That is, the number of dots that must be drawn on the frame memory is twice the number of dots in the original pattern.

For each of these dots, the drawing position is calculated to determine where in the frame memory the dot should be drawn, and each dot is stored in the frame memory for each access unit of the frame memory consisting of multiple dots. The data of the corresponding dot is determined by performing a modification operation on the data that is currently displayed and then writing it into the area.

[Problem that the invention seeks to solve]

In the conventional graphic display device control circuit as described above, it takes n2 or more drawing cycles to draw a graph ink character of nXn dots.
2 compared to a character generator type character display device.
This causes a difference in drawing speed of nearly an order of magnitude.

A character generator-type character display device divides the display area of the display device into a matrix of small dots and assigns patterns according to codes, and is a very effective control method in systems that require high-speed single display. Compared to graphic character drawing methods, this method has drawbacks such as the inability to control characters with angles and inclinations, and the inability to freely select the starting point of a single character.

The present invention was made based on such circumstances, and its purpose is to provide a graphic display device with increased drawing speed.

[Means for solving problems]

In order to achieve such an object, the present invention provides a graphic display device having a function of drawing a pattern in eight directions dividing a specified rectangular pattern in units of 45°. The present invention is provided with a pattern register that develops into a directional pattern, and a means for using the pattern register to execute pattern drawing on the frame memory in units of access to the frame memory consisting of a plurality of dots. .

[Effect]

In this way, by providing the pattern register, it becomes possible to divide and read the pattern register data in units of frame access, and to execute writing to the frame memory in each unit.

Therefore, the pattern drawing decision to the frame memory is
It is possible to draw multiple dots at once instead of dot by dot as in the conventional method, and the drawing speed can be increased.

〔Example〕

FIG. 1 is a schematic block diagram illustrating one embodiment of a graphic display device according to the present invention.

First, a drawing designation pattern 9 consisting of 8×8 dots for drawing a graphic character, the drawing direction of the pattern, and the leading dot to be drawn are specified by a CPU (not shown). The designation of the drawing direction is shown in Fig. 4(a).
As shown in FIG. 2, it is composed of a pattern development command 14 and a drawing direction designation section 15. The drawing direction designation section 15 is, for example, 3
It consists of bits, which allow one of eight directions to be specified at 45° intervals.

The data in the drawing direction specifying section 15 in which the drawing direction is designated is stored in the drawing direction selection circuit 4.

The data in the drawing direction selection circuit 4 is output to the pattern register 1 via the pattern development readout control circuit 2. Further, at this time, data from the expansion start point selection circuit 6 is also output to the pattern register 1. The data of the expansion start point selection circuit 6 is data for calculating the expansion area on the pattern register 1, together with the above-mentioned drawing direction data and the like.

The output from the pattern development readout control circuit 2 to the pattern register 1 is performed by a timing signal from the pattern write control circuit 3. Also.

The pattern writing control circuit 3 also outputs interpolated data as the case may be. As will be described later, this interpolated data is stored in the pattern register 1 in two different numbers of dots.
Since the register selection system is composed of register selection systems, the data is output to the register system having more dots than the number of dots in the drawing designation pattern 9.

The pattern register 1 is configured such that drawing data 10 is stored in a development area 11. The drawing data 10 is stored in a diamond-shaped area of 16 dots vertically and 15 dots horizontally. As a result, as shown in FIG. 3(b), each horizontal 8-bit pattern of the drawing designation pattern 9 is changed to each horizontal 8-bit pattern of the drawing pattern 10, as shown in FIG. 3(c). It is now possible to correspond to

As shown in FIG. 4(c), the drawing data 10 includes a development area 17 in which the specified drawing designation pattern 9 is embedded as is, and a development area 17 in which the drawing designation pattern 9 is embedded at an angle. The data is stored in two register systems having an area 17.

Each development region 17, 18 has a starting point 16 that is a starting point for development in each direction. This starting point 1
The data corresponding to 6 is stored in the starting point selection circuit 6. Using this starting point 16 as a reference, the development area on the pattern register 1 is calculated based on drawing direction data and data on the size of the pattern specified for development.

The drawing data 10 stored in the pattern register 1 is extracted and read out by the drawing read address control circuit 7 for each frame memory access unit based on the drawing data selection circuit 8. The readout control of the drawing data selection circuit 8 is executed in response to instructions from the pattern development readout control circuit 2.

As shown in FIG. 3(d), the frame memory access is divided into divided blocks 12 and 13 by specifying the drawing start point of the frame memory, and is accessed for each frame in each divided block. They are accessed sequentially.

In such a configuration, a specific example of pattern expansion into the pattern register 1 will be described below.

The drawing direction when drawing graphic characters is designated by the CPU, and this designation is included in the pattern development command 14 shown in FIG. 4(a).

To specify 8 directions divided into 45° directions, use the fourth
As shown in Figure (a), the drawing direction specifying section 15 only needs to have 3 bits. With these three bits, eight directions can be specified, as illustrated in FIG. 2(b). Note that this drawing direction designation section 1
Data 5 is stored inside the drawing direction selection circuit 4 in FIG.

The pattern development area of pattern register 1 is shown in the same figure (Q).
As shown, #2.4, 6.8 development area 17 90
Deployment area in the degree direction and #1 and 3 shifted by 45 degrees
, 5.7 development areas 18 are divided into two types and 8 direction development areas.

Each development area 17,18 has a starting point 16 of development in each direction.
has. This starting point is determined by hardware as fixed data for each drawing direction, and is stored inside the starting point selection circuit 6 shown in FIG.

The area required when executing pattern development in pattern register 1 is an area equal to the number of dots of the specified pattern in the 90° direction, and 45 degrees from this direction.
°For the shifted direction.

This area is equal to twice the number of dots in the specified pattern.

90'' direction, Fig. 4 (b) (7) #0,2゜4
．． For direction #6, the specified pattern is embedded as is, and for directions #1, 3, 5°7, the pattern is embedded and the dots located in between are interpolated at the same time. There is a need to.

In this embodiment, as shown in FIG.
This is realized using two register selection systems: a 4.6 matrix selection system and a #1,3°5,7 matrix selection system.

First, considering an 80.2, 4.6 matrix selection system with 906 directions, the pattern directions are #0, #4. Control is divided between #2 and #6.

That is, in the #0 and #4 directions, pattern expansion control can be executed by supplying data to Conversely, supply data to yo-yn and x.

By supplying a write control signal to x0, pattern expansion control can be executed.

As you can see, #0 and #4 directions or #2 and #6
The difference in direction is that the dot development position of the specified pattern is reversed at the same time that the development start point becomes the diagonal point.

The directions #1, 3, and 5°7, which are shifted by 45° from the 90° direction, are also divided into the #1 and #5 directions, and the #3 and #7 directions, and the same control as in the above-mentioned directions is required. In addition, in this direction, there are empty dots between the dot positions where the actual pattern should be developed, so these must be interpolated. For such dots, for example, yo
The dot located between and yl is interpolated by pushing the pattern developed at the yo position. Therefore, a method is adopted in which the write control signal supplied to yo and the data of XQ-Xn are also supplied to the register bit for this dot to be interpolated, thereby uniquely determining the register data.

FIG. 6 shows the basic structure of each register bit of the pattern register 1 for controlling the pattern expansion method.

ddo, ddz, dda, dde (ddx, dda.

dds, dd7) are direction control signals instructed by the drawing direction specifying section, and d Iy dn-11dJ+ dn-
J is.

This is data to be written in each direction. WYI and WX
J, each is a write control signal controlled from the drawing direction.

In this circuit configuration, the direction control signal for direction #0 is ddo, the data signal d at this time is active, and the write control signal WYl is active.

Similarly, the direction control signal for direction #2 is d d'z, the data is d, the write control signal is WXJ, and #4
For #6, the combination is dd4°dn-J, WYt, and d de, dn-JIW X J.

Control is executed for #1, 3, and 5.7 using a similar circuit configuration. However, in this direction, interpolation bit control is also performed.

Each register bit is a combination of the basic configuration shown in Figure 6(b), and has three controls: #0, 2, 4.6 direction, #1.3°5.7 direction, and control as an interpolation bit. This is achieved by combining circuits that perform this.

Next, an example of reading register data from the pattern register 1 and writing to the frame memory when a pattern drawing command to the frame memory is received will be described below.

When accessing the frame memory, it is executed in units of multiple dot configurations. This is determined by the screen configuration, and the CP
It is designated as initial data from U to the graphic display control circuit.

On the other hand, all the patterns developed in the pattern register 1 have a development start point 16, and depending on the data of this development start point, the drawing direction data, and the size of the pattern specified to be developed, the pattern is developed in the pattern register. Area can be calculated.

This calculated development area is, as shown in FIG.
t +i-X t”L+-11Y k-Y k”n (
7) Given as a region.

On the other hand, the CPU gives the drawing start point on the frame memory, which is the starting point 16 of the expansion.
This specifies where on the frame memory the drawing should start.

How the pattern register should be divided into frame memory access units is uniquely determined depending on the relationship with the frame memory access units.

The frame memory access unit is composed of j dots.
For the starting point of expansion of (Xl+J, Yb), if the drawing starting point is given as the leftmost position of the frame memory access unit, the data in the given pattern register is
The area is divided into two frame memory access units: I to X1+J-1 and Xt+ to Xl+2J-1.

Also, for (X1+J, Yh), if the drawing start point is the rightmost point of the frame memory access unit, the data in the pattern register is from X1+1 to X1÷J.

It is divided into two areas from X1+J+1 to Xl+2J.

For (X I+ J , Y h ), if the drawing start point is not at both ends of the frame memory access unit but at an intermediate point, the area is divided into three.

In this way, data in the pattern register is divided into frame memory access units and read control is performed.

The drawing data selection circuit 8 receives an instruction from the pattern development readout control circuit 2 and executes it.

As explained above, first, depending on the hardware configuration, C
In accordance with the pattern development command from the PU, the pattern data given thereafter is developed into the pattern register one word at a time, each time the pattern data is given.First, the pattern register data is developed based on the pattern drawing command to the frame memory. , division and reading are performed for each frame memory access unit, and writing to the frame memory is executed for each unit.

Therefore, the pattern drawing decision to the frame memory is
Multiple dots can be drawn at once rather than dot by dot, making it possible to speed up the drawing speed.

〔Effect of the invention〕

As is clear from the above description, according to the graphic display device according to the present invention, the drawing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an embodiment of a graphic display device according to the present invention, FIG. 2 is a conceptual explanatory diagram showing an example of a conventional graphic display device, and FIG.
7 to 7 are block diagrams showing details of an embodiment of each part of the graphic display device according to the present invention, FIG. 3 is a diagram showing a pattern development method, and FIG. 4 is a drawing direction designation and pattern development. FIG. 5 is a diagram showing the matrix selection system in pattern expansion, FIG. 6 is a diagram showing the register bit configuration of the pattern register, and FIG. 7 is a diagram showing the division method of frame memory access units for pattern register reading. It is a diagram. DESCRIPTION OF SYMBOLS 1... Pattern register, 2... Pattern development read control circuit, 3... Pattern register write control circuit, 4
... Drawing direction selection circuit, 5... Drawing start point selection circuit,
6... Expansion start point selection circuit, 7... Drawing read address control circuit, 8... Drawing data selection circuit, 9... Drawing specified pattern (example), 10... Drawing data (example), 1
1...Development area, 12...Divided block 12.13
...Divided block 13.14...Pattern development command, 15...Drawing direction designation part, 16...Start point of development,
17...#0゜2.4.6 Development area, 18...#1
, 3, 5.7 development area, 19... So, 2, 4, 6 direction control circuit, 20... #1, 3, 5, 7 direction control circuit, 21... interpolation bit control circuit, 22 ...Register bit, 23...Frame memory access unit.

Claims (1)

[Claims] 1. A graphic display device having a function of drawing a pattern in eight directions divided by a specified rectangular pattern in units of 45 degrees, including a pattern register that develops the specified rectangular pattern into a pattern in a specified direction; A graphic display device characterized in that a means is provided for drawing a pattern on a frame memory in units of access to a frame memory composed of a plurality of dots, using the pattern register.