JPH01155471A - vector processing device - Google Patents

Abstract

PURPOSE:To shorten a processing time and to improve the performance of an instruction processing by making access to a main memory device only for one time in case of making access successively to the same address on the main memory device for plural times. CONSTITUTION:A detection circuit 9 detects a case where a vector load address store instruction makes access to the same address on the main memory device MS24. In case of a simple load store instruction, the address of operand data is decided by VAR representing the sum of a leading element address and an element interval VIR. Therefore, the access is recognized as the one to make access to the same address on the MS under a condition VIR=0. A request control circuit 10 changes the number of memory requests to be sent to a main memory control unit SCU23 by indication from the circuit 9. In other words, in case of making access to the same address on the MS, only one request is sent, not sending 64 requests successively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a vector processing device that performs high-speed processing of matrix calculations that appear in scientific and technical calculations, and particularly relates to a vector processing device that processes the same address on a main memory multiple times in succession. The present invention relates to a vector processing device suitable for efficient access.

[Conventional technology]

A vector processing device has a vector processor that stores a series of vector data read from the MS and vector data that is an intermediate result of operations between a main memory (MS) and an arithmetic unit.
It has a register (VR). For vector data on VR, there is a mask that indicates whether each element is valid or invalid.
A vector mask register (VM
R) is held. The mask bits are vector
It is generated by data comparison, etc. and is held in the VMR, and is referenced in parallel when reading and writing to the VR.
It is used to enable or disable processing such as vector data calculation, load, and store for each element.

In the conventional vector processing device,
As described in No. 8571, when accessing the same address on the MS multiple times in succession, the data from the first access is retained in the case of a load, and the vector address is used for subsequent accesses. Access is performed while avoiding bank conflicts by modifying a part of the data, and access is speeded up by invalidating the read data.

However, in the case of a load or store controlled by a mask, there is no way to recognize the first valid element or the last valid element, and consecutive accesses to the same address inevitably reduce throughput due to bank contention. Ta.

[Problem that the invention seeks to solve]

The above conventional technology does not take into consideration continuous access to the same address controlled by a mask, and does not take into account continuous access to the same address controlled by a mask. There was a problem in that throughput decreased during storage processing.

An object of the present invention is to avoid bank conflicts on the MS by converting multiple consecutive accesses to the same address on the MS into one access in load/store processing controlled by a mask, and to achieve efficient access. The object of this invention is to realize a vector processing device that enables the following.

[Means for solving problems]

The above purpose is to recognize the first valid element or the last valid element from mask bits that enable or disable vector data element-wise, and
This is accomplished by configuring the load-store pipe to perform only 8 accesses.

Therefore, (1) a circuit that recognizes that the access is to the same address on the MS based on the addressing specification of the vector load/store instruction and the contents of the vector address register, and (2) (3) a circuit that converts additional information so as to invalidate data other than the element number held when referencing the mask; (4) a circuit that holds the element number of the valid element or the last valid element; In the load process, a circuit holds the first valid data and sends the same data held for all elements to VR;
) In the store process, select the last valid data among all the valid data transferred from VR and store it in the MS.
A writing circuit is provided.

[Effect]

Vector load/store instructions include a simple a-do store instruction that linearly accesses the MS depending on the contents of the vector address register (VR) and vector φ increment register (VIR), and the VR general instruction. An indexed load/store instruction that non-linearly accesses the MS by means of an index register (arbitrary VR) is executed.

The circuit that recognizes the access type recognizes that the access is to the same address on the MS when the VI is -101 in the case of linear access, that is, the element interval value lo1. In addition, in the case of indexed load/store instructions, the index is empty, empty, empty register (SR).
), M9 recognizes that the access is to the same address on the MS by being a literal (LIT).

The mask generation circuit is provided with a counter, which is counted up every time one mask bit is generated.

When the mask bit first reaches 111, the value of the counter is the first valid element number register (referred to as FVER).
is captured and retained until the mask is referenced. On the other hand, each time the mask bit becomes Ill, the value of the counter is taken into the last valid element number register (referred to as LVER), and the number of the last valid element is left when mask generation is completed.

A code is transferred to the mask reference circuit from the circuit that sets the access type to gR, and when accessing the same address on Ma continuously, only the element indicated by FVER or LVER is read to the MS. Control is performed to write. pvg in case of a-do processing
Only the element indicated by a is sent to the main storage control unit (SCU) with additional information that enables MS access added thereto.

In the SOU, data is read from the MS only for the elements with the additional information and held in the register (.The data is transferred to the VR along with the mask bit, and data is written only for the valid elements. Store In the case of processing, only the element indicated by LVgR is added with additional information that enables MS access and sent to the SCU.The SCU writes data to the MS only for the element with the additional information.The data is masked.・Of the data sent from the bit and KvfL, only valid elements are set in the register, and this is the last remaining data.

The a-do store pipe has a register that holds the data corresponding to the first valid element of the load process), and in the above load process, for the element of mask bit 11', the data is sent to the VR. Send.

In addition, the load/store vibe has a register that holds data corresponding to the final valid element of the store process.
If the mask bit associated with the data read from the box is t1+, the data read from the VR is set. Then, when VRgt and protrusion are completed for all elements, data corresponding to the last effective element remains, so this data is sent to the SCU.

〔Example〕

FIG. 1 shows a VR vector processing device to which the present invention is applied.
FIG. 3 is a diagram showing a peripheral configuration. In Figure 1 - (18 is V
R, 19 is VM, 25 is 8CU, 24 is MS.

In this embodiment, a vector processing device using an element parallel control method will be described. Therefore, both VR18 and VMRI9 are divided into four parts corresponding to the number of parallel elements of four. VR18
, VMRI 9, each divided unit is composed of 64 elements, and a total of 256 elements can be processed at once.

In the case of normal vector/a-word instruction processing, the request control circuit 10 handles 64 memory requests in 5CU25.
Issued to. Four mask bits are read out from the 7MR 19 for one memory request, passed through the additional information conversion circuit 20, and sent to the 8CU 23 as memory request additional information. At this time, an order to invalidate the memory request is added to the element of the mask bit fol. 8CU25 makes a read request t-Ms only for the element corresponding to 111 of the 4 mask bits for each memory request t-Ms 24
Send to. Data read from Ma (up to 4 pieces)
is passed through the 5CU 23 and set in the register 25. 1
When all the data corresponding to the memory request is collected, the data held in the register 23 is sent out and written to the VR 18 through the selector 17. The data writing position is indicated by an element number counter (E) 2. gR2 starts from the initial value 101 and is counted up by 1 by the counter 3 for each memory e request, and indicates the entry on the VR 18 to which the data read in the next memory request is to be written. The above operation is repeated 64 times to complete the loading process of 256 elements.

Similarly, in the case of normal vector store instruction processing, the request control circuit 10 handles 64 memory requests in 5C
Issued to U25. Four mask bits are read from the VMRI 9 for one memory request, and sent to the 8CU 23 through the additional information conversion circuit 20. At this time, an order to invalidate the memory request is added to the element of mask bit Igl.

On the other hand, data is read from the entry on VRI a obtained by subcoding the contents of ER,2 by the decoder 8, and is set in the register 21. The data is then sent to the 8CU 25 in synchronization with the memory request. The 5CU 23 writes the received data to the MS 24 based on the memory request. The above operation is repeated 64 times to complete the storage process for 256 elements.

The detection circuit 9 detects when a vector load/store instruction makes the same access on M8. In the case of a simple a-do store instruction, the address of the operand data is determined by the sum of the VA value indicating the first element address and the VI value indicating the element interval value. Therefore V I R-'o'
Under this condition, it is recognized that the same address on M8 is to be accessed. In the case of an indexed load store, the operand address is V indicating the first element address.
It is determined by the sum of AR and an index indicating an offset from the first element. Therefore, it is recognized that the same address on the MS is to be accessed under the condition that SR1 or ITt- is specified as the index.

The request control circuit 10 changes the number of memory requests sent to the 5CU 25 according to instructions from the detection circuit 9. However, when accessing the same address on the MS, only one request is sent instead of 64 consecutive requests. In the case of a vector load instruction, if 11" exists in the mask bit sent from VMRI9,
A memory request is sent to the 5CU 23jC for the first time. After the memory request corresponding to the first valid element 1g is issued, no memory request is sent even if there is a valid element. On the other hand, the compliment signal 14 of the VRI 8 is sent out 64 times for each parallel element. Actual writing is controlled by the VMRI 9, and data is written only for valid elements. For vector store instructions,
A memory request is sent to the 5CU 23 in response to the last +1+ of the mask bits sent from the VMRI 9. Therefore, for 64 VMR reads, a memory request is sent only once for the final valid element parallel. On the other hand, reading of the V-box 18 is performed 64 times for each parallel element. In either vector load or vector store, E'BI2 indicating the entry to be accessed on the 4V 318 is counted and accepted by 1 for each parallel element.

That is, the control signal 26 is sent from the request control circuit 10 so that the VR 18 is accessed corresponding to all elements.

In the case of normal vector load/store instruction processing, the additional information conversion circuit 20 adds an order for disabling MS access to the mask p1o1 element. If the M8 access is to the same address, in addition to this operation, an operation is performed to add an MS access order to the subsequent valid elements (from the first valid element in the a-card processing), and store processing is performed. Then, an operation is performed to add an order for invalidating MS access to the valid element before the last valid element.

The mask generation circuit 1 operates when a mask generation instruction such as a comparison instruction is executed, and stores mask bits obtained based on the execution result in the VMRI 9. During this operation, it is possible to detect the first valid element and the last valid element, so the first valid element number t-FVER5K and the last valid element number are set to L.
Each is stored in VER6. Tsumashi, first mask φ
When the bit reaches 111, the value of ER2 indicating the element number being processed is transferred to the FVE box 5 and held there. - flat FV
After ER5 is set, subsequent mask bits 11 are inhibited from being set. mask bit is 111
Each time the value of ER12 is reached, the value of ER12 is transferred to LvER16 and held. When the mask generation process is completed for all elements, the element number of the final valid element is left in I, VER6.

The following describes processing when a vector load/store instruction accesses the same address on the MS multiple times.

A mask generation instruction is executed prior to the vector load/store instruction to generate a mask to be used in the subsequent load/store and store the first valid element number in FVffR5 and the last valid element number in LYER6.

FVER5 is conveniently used for vector a-do instructions. FV
The value of ER5 is given to the decoder 8 through the selector 7, and the mask 4 bits for one element difference sequence including the first valid element are set to V.
The data is read from the MR 19 and transferred to the additional information conversion circuit 20. The additional information conversion circuit 20 adds an order for disabling MS access to elements other than the first valid element.

For example, as shown in Figure 2, if the mask bit is '01101 and the value of FVER5 is 11 years, the order to be added is '
1011'. The request control circuit 10 sends the menu/request only once in response to the element parallelism by 5CU25.
Issued to. The 8CU 25 refers to the order, accesses the MS 24 only for elements to which no invalidity instruction has been added, and reads data corresponding to the first valid element.

The read data is set in the register 25 through the 5CU 23. At that time, the data is expanded into four elements arranged in parallel. The register 25 continues to hold the data after it is set by the set signal 2B. During this time, the VB control circuit 11 updates E2 by the set signal 26, and writes the same data to the register 25 for all valid elements of VR by the write signal 14. When writing, the value of VM box 19 is reflected, and the same data as that at the access address on M8 is written only for the element of mask bit 111.

Vector store instructions use LVER6. LV
The direct signal of ER6 is given to the decoder 8 through the selector 7, and the mask 4 bits for one element difference sequence including the final effective element are set to V.
The data is read from the MR 19 and transferred to the additional information conversion circuit 20. The additional information conversion circuit 20 adds an order to disable M8 access to elements other than the final valid element.

For example, when the mask bit is '0110' as shown in FIG. 3, the order to be added is '1101'.

The request control 10 issues a memory request to the 5CU 25 only once in response to the element parallelism. 8C
U23 refers to the order, accesses MS24 only for elements to which no invalidity instruction has been added, and writes data corresponding to the final valid element. This data is the data indicated by LVER6 among the four data read from VRI 8 and set in register 21 in synchronization with reading from VMR 19. As a result, the same result as when all valid elements are written is left at the access address on the MS.

According to this embodiment, by processing continuous accesses with a mask to the same address on M8 from prime number 0 to element number 255 as a single access, It is possible to avoid a decrease in the throughput of store instructions.

〔Effect of the invention〕

According to the present invention, when the same address on an MS is accessed multiple times in succession in processing a masked vector load-during-store instruction, processing time is shortened by accessing M8 only once. It is possible that
Instruction processing performance is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 and FIG.
The figure is an explanatory diagram showing an example of mask bits. 1 - mask generation circuit, 2 - element number register, 5 - first valid element register, 6 - last valid element register,
9...Detection circuit, 10-Request control circuit. 11・VR control circuit, 19...Vector mask・
Register, 20--additional information conversion circuit. Fig. 1 Fig. 9 Failed specimen Fig. 2 Broom 3 Document of drawing procedure amendment (spontaneous) Indication of the case 1988 Patent Application No. 314058 Name of the invention Vector processing device Person who makes the correction Person and Section 1 Patent applicant name Name Cs+o+stock Company Hitachi, Ltd. (Fossil 1 stone) Target of agent amendment Drawing (all drawings) Contents of amendment Attachment page 1 9-0. Kenden Meku almost 2 drawings raw cotton 7 plain simple 50! tviyrp7TfT* element

Claims (1)

[Claims] 1. A main memory that stores vector data, multiple arithmetic units, multiple vector registers that hold intermediate results of operations, and reads and writes vector data from and to the main memory. Multiple load stores
A pipeline, multiple mask registers that specify whether operations and main memory access are enabled, and their generation and
In a vector processing device consisting of a reference control circuit, a circuit detects that data to be accessed has the same address based on the addressing specification of the vector load/store instruction and the contents of the vector address register, and A circuit that recognizes the first valid data or the last valid data and holds that element number, and additional information that invalidates data other than the element number held when referencing the mask. A circuit that performs the conversion, a circuit that holds the first valid data read from main memory and sends the same data for all elements to the vector register, and a circuit that holds the first valid data read from main memory and sends the same data for all elements to the vector register. It is configured by a circuit that selects the last valid data from among all the elements that have been sent and writes it to the main memory, and it is a main memory that selects the last valid data from among all the elements that have been received and writes it to the main memory multiple times consecutively to the same address in masked vector load/store instruction processing. A vector processing device characterized by speeding up vector load/store processing by reading or writing only once.