JPH0116060B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a low-cost, high-precision digital-to-analog converter for converting digital signals used in various communication devices and control equipment into corresponding analog signals. Conventionally, one method to improve the nonlinear error of digital-to-analog converters (hereinafter referred to as DAC) is to
An output that satisfies linearity is selected from among the outputs of high-resolution DACs that do not satisfy linearity (for convenience of explanation, this will be referred to as the original DAC), and the digital input of the original DAC is selected to obtain the selected output. is stored, and the digital input of the original DAC is recalled using the digital input corresponding to the output level.
is used to create a DAC that satisfies linearity, although the resolution is equivalently lower than that of the original DAC.
There is a so-called digital trimming method. A DAC using this method requires the following characteristic conditions for the original DAC. In other words, the output is selected appropriately from among the discrete outputs of the original DAC and
Although the resolution is lower, linearity is satisfied.
To obtain a DAC, the original DAC must have this series of appropriate levels. The nonlinear error of the original DAC is converted to the nonlinear error of the DAC to be obtained.
Figure 1a shows the possible range of output levels when the signal is held within 1 LSB. In the figure, A is the ideal level of the DAC to be obtained, B is the ideal characteristic of the original DAC, and C is 1LSB of the DAC to be obtained. In FIG. 1a, the center line A is the ideal output, and at least one level is required in the shaded area within ±1/2 LSB with respect to this ideal value. As is clear from the figure, the probability that this output exists is 1−
(1/2) ⁴ ≒93.75%, so the above conditions cannot be completely guaranteed. In order to completely guarantee this, as shown in Figure 1b, the ±
Nonlinear errors must be kept within 1/2LSB. In FIG. 1b, the probability of obtaining a predetermined level is 1-1/4×0×1/4×1/2=1, and only then is it completely guaranteed. In other words, in general, if the element deviation of the unit elements constituting the load element in a DAC is the same and the resolution is increased, the absolute value of the error will decrease accordingly, so even if the element deviation does not satisfy linearity in the desired DAC resolution, , the original DAC can be
It is possible to suppress the error within ±1/2LSB of the DAC that is intended to obtain the error, and linearity can be satisfied by the above-mentioned trimming. However, in order to suppress the error within ±1/2LSB of the DAC that we are trying to obtain by increasing the resolution, we have to increase the unit capacitance, and in the end, the increase in the number of unit elements (n
times) element deviation

[Formula]] is the only way to reduce the error by reducing the element deviation. Figure 2 shows the relationship between the device deviation of a unit element and the output error obtained by Monte Carlo analysis for a simple capacitance DAC configured by weighting the unit capacitance as 1, 2, 4, 8, etc. of
When changing from 12 bits to 14 bits, that is, the unit element value is 4
It can be seen that the error when doubled is equal to the error when the element deviation is halved. Therefore, completely guaranteeing the trimming by the method described above is nothing more than guaranteeing the desired linearity, and there is no point in trimming. The effectiveness of digital trimming is to obtain a DAC with the highest possible resolution and guaranteed accuracy from an original DAC with poor characteristics through a simple trimming operation, whereas in the conventional case, it is not always effective as described above. There was a problem that it could not be done. Furthermore, the existence of an appropriate level is stochastic, and the more the nonlinearity of the original DAC is to be avoided, the more complicated and difficult the correction work to find an appropriate level becomes. In order to perform digital trimming as described above, the trimming work becomes complicated and there is a problem that effective trimming cannot be performed. Furthermore, in order to solve this problem and improve trimming efficiency as much as possible, the configuration shown in FIG. 3 has been used in the past. In Figure 3, 1 is a digital input signal terminal, 2 is an analog output signal terminal, and 3 is a digital input signal terminal.
4 is an input signal terminal of a correction DAC, 4 is an analog adder/subtractor, 5 is an original DAC, and 6 is a correction DAC. Former
The error of the DAC is generated by the correction DAC, and the error is removed by the adder/subtractor.
In this case, the following conditions are required for the correction DAC. In other words, assuming that there is no error caused by the adder/subtractor, the characteristics of the correction DAC are such that the step value is 1 LSB of the DAC to be obtained, and the error is less than ±1/4 LSB, and the full scale is less than the original DAC.
must be greater than the maximum error of This is accuracy,
The implementation of this correction DAC is problematic because the resolution of the correction DAC must be set in consideration of the maximum error of the original DAC. Furthermore, errors in the analog adder/subtractor are a major problem as they become the basis for achieving higher precision through trimming. Even with the conventional methods described above, the number of error factors such as correction DACs and adders/subtractors increases, and it is difficult to reduce these errors in terms of circuit technology, so there is a limit to how high precision can be achieved through trimming. There was a problem that I couldn't do it. In order to solve these problems, the present invention has developed a DAC that generates an output for the upper digit, a DAC that generates an output for the lower digit, and a DAC that adds the outputs of these two DACs and outputs the result from the lower digit to the upper digit. It is characterized by a configuration in which the DAC output when carrying to a digit always decreases, and its purpose is to reduce the allowable value of the nonlinear error of the original DAC in order to achieve the desired accuracy, and to correct it. regularize the amount,
Enables effective and easy digital trimming,
The aim is to make the DAC smaller and faster. FIG. 4 is a configuration diagram for explaining the basic principle of the present invention. 1 is a digital input signal terminal, 2 is an analog output signal terminal, and 7 is an upper DAC that generates the output of the upper digit (this is called M DAC). 8 is the lower DAC that generates the output of the lower digit (this is referred to as L DAS
), 9 is an analog adder, and 10 is a code converter. The full scale of L DAC is 1LSB of M DAC.
If you make it larger and satisfy the linearity in the resolution of L DAC, you can change from L DAC to M DAC.
A characteristic that decreases when carrying is obtained is obtained. An example is shown in FIG. 11 is the input/output characteristic of the L DAC, 12 is the input/output characteristic of the M DAC, 13 is the shift amount of the digital input, 14 is the input/output characteristic of the DAC obtained by shifting the digital input, and 15 is the ideal characteristic of the original DAC. be. As shown in Figure 5, the overall output characteristic is that a jump in the negative direction occurs at the point where the carry from L DAC to M DAC occurs.
The characteristic curve of L DAC is superimposed with that point as the starting point. By shifting the digital input by the amount indicated by the arrow 13, a characteristic satisfying the linearity 14 can be obtained. This digital input is shifted by a code converter 10 (FIG. 4). The shift of the digital input is, for example, the code 01000 surrounded by a broken line among the digital inputs in FIG.
This can be done by masking analog outputs corresponding to 01001, 01010, 10000, 10001, etc., and sequentially shifting and supplementing the masked codes as shown by arrow 13 in FIG. For example, 01011 → 01000, 01100
→01001,01101→01010,01110→01011,01111→
Just convert the code from 01100, 10010 to 01101, etc. FIG. 6 shows a specific embodiment of the present invention,
1 is a digital input signal terminal, 2 is an analog output signal terminal, 16 is a reference voltage terminal, and 17 is an analog switch. In addition, the circuit configuration is such that the outputs of an L-bit DAC formed by a capacitor array arranged in a binary weighted manner corresponding to the bits of the digital input and the output of an M-bit DAC connected in the same manner are mutually coupled by a capacitor _Cc . be. In this circuit, the value of the coupling capacitance C _c is changed from the right terminal to the LSB side.
If the capacitance value including the DAC capacitance string is equivalently a unit capacitance, that is, C _c = 2 ^L / 2 ^L - 1 × [unit capacitance], then a normal capacitance with a resolution of L + M bits
Operates as a DAC. This is the output of L DAC.
This is because it is multiplied by 1/2 ^L by C _c and added to the M DAC output, and the analog addition of the M DAC output and the L DAC output is realized by C _c , so the value of this C _c is the L DAC output. This determines the slope of the input versus output characteristic of . That is, if C _c is larger than 2 ^L / 2 ^L - 1 × [unit capacity], the slope will be larger than ideal,
Even if the error occurring in M DAC is taken into consideration, by setting C _c appropriately, it is possible to ensure that the change caused by the carry from L DAC to M DAC always occurs in the negative direction. Therefore, the coupling capacitance C _c should be set to the ideal value, i.e.
If it is set appropriately larger than 2 ^L /2 ^L -1 x [unit capacity], there will be no jump in the positive direction at the joint between the outputs of L DAC and M DAC. Keep the nonlinear error of L DAC within 1/2 LSB of the resolution of 2 ^L , and
If the value of C _c is set to cover the error of the DAC, there will be a level in the analog output that maintains linearity corresponding to 1LSB of the L DAC, and linearity can be obtained from the digital input. original like
By converting to the digital input of the DAC,
A DAC that satisfies linearity can be obtained. As explained above, L DAC in the original DAC
satisfying only the linearity of L DAC to M
For example, by setting the value of C _c shown in Figure 6 to be larger than the ideal value, try to obtain such that the output level always decreases when passing to the DAC.
It is now possible to completely guarantee that the DAC level exists, and the conditions of the original DAC that enable digital trimming are the element deviation of the load element, and the analog adder greatly reduces errors and allows efficient digital trimming. can be done. Also, the amount of trimming is from L DAC to M
In principle, it can be obtained by simply adding the difference when the digits go up to the DAC in sequence.
Trimming work becomes easier. Furthermore, in the case of a capacitive column DAC, the element value can be reduced by the amount that can alleviate the load element deviation, thereby making it possible to reduce the area and increase the speed. In principle, L should be used for more complete correction.
The number of digits from DAC to M DAC, i.e.
It is sufficient to store the number of bits of MDAC, that is, the ^2M correction amount, and the storage circuit for this purpose can be reduced, which also has the advantage of making it possible to reduce the size and area.

[Brief explanation of drawings]

Figure 1 is a diagram showing the nonlinearity of the original DAC and the possibility of trimming in a conventional DAC. Figure 2 is a diagram showing the results of Monte Carlo analysis of the element deviation and DAC nonlinear error of a capacitive string DAC. A configuration diagram of a conventional digital trimming DAC, Figure 4 is a configuration diagram showing the basic principle of the DAC of the present invention, and Figure 5 is a configuration diagram of the DAC of the present invention.
FIG. 6, which is a diagram for explaining high precision, is a circuit diagram of an embodiment of the present invention. 1... Digital input terminal, 2... Analog output terminal, 3... DAC input signal terminal for correction, 4...
...analog adder/subtractor, 5...original DAC, 6...correction DAC, 7...M DAC, 8...L DAC,
9...analog adder, 10...code converter,
11...L DAC output, 12...M DAC output, 13...Digital input correction amount, 14...
... Characteristics according to the present invention, 15 ... Ideal characteristics of the original DAC, 16 ... Reference voltage terminal, 17 ... Analog switch.

Claims (1)

[Scope of Claims] 1. A first digital-to-analog converter that generates an output of the upper digits and a second digital-to-analog converter that generates the output of the lower digits; In a digital-to-analog converter that obtains an output by adding the output and the output of a second digital-to-analog converter, the amplitude of the full-scale output of the second digital-to-analog converter is equal to the value of 1 LSB of the first digital-to-analog converter. The input signal is always larger than that of the second digital-to-analog converter, and the input signal is configured such that the relationship between the digital input signal and the analog output signal is approximately linear along an ideal characteristic with a slope equal to the relationship in the second digital-to-analog converter. A digital-to-analog converter comprising a code converter for shifting a desired value and inputting the shifted value to first and second digital-to-analog converters. 2. The output point of a second digital-to-analog converter composed of a binary-weighted capacitance string and an analog switch, and the output of a first digital-to-analog converter having the same configuration as the second digital-to-analog converter. The equivalent capacitance of the second digital-to-analog converter including the coupling capacitance from the output point of the first digital-to-analog converter is greater than the unit capacitance of the first digital-to-analog converter. 2. The digital-to-analog converter according to claim 1, wherein the value of said coupling capacitance is set to be large.