JPH01162474U - - Google Patents
Info
- Publication number
- JPH01162474U JPH01162474U JP5654888U JP5654888U JPH01162474U JP H01162474 U JPH01162474 U JP H01162474U JP 5654888 U JP5654888 U JP 5654888U JP 5654888 U JP5654888 U JP 5654888U JP H01162474 U JPH01162474 U JP H01162474U
- Authority
- JP
- Japan
- Prior art keywords
- ram
- data
- dual port
- transferred
- elevator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims description 6
- 230000005856 abnormality Effects 0.000 claims 4
- 238000001514 detection method Methods 0.000 claims 3
- 230000001105 regulatory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Indicating And Signalling Devices For Elevators (AREA)
- Multi Processors (AREA)
Description
第１図は本考案の一実施例のプログラム実行の
ジエネラルフローチヤート、第２図はマイコンの
ハードウエア構成図、第３図は本考案の他の実施
例のプログラム実行ジエネラルフローチヤートで
ある。
１３，２３…ＲＡＭ、３０…デユアルポートＲ
ＡＭ。
Fig. 1 is a general flowchart of program execution in one embodiment of the present invention, Fig. 2 is a hardware configuration diagram of a microcomputer, and Fig. 3 is a general flowchart of program execution in another embodiment of the present invention. . 13, 23...RAM, 30...Dual port R
A.M.
Claims (1)
イコン相互間のデータ通信にデユアルポートＲＡ
Ｍを使用したエレベータにおいて、 個々の前記マイコンにＲＡＭを備え、エレベー
タ制御プログラムの実行周期毎に前記デユアルポ
ートＲＡＭのデータを前記ＲＡＭに転送、及び前
記ＲＡＭのデータを前記デユアルボートＲＡＭに
転送すると共に前記エレベータ制御プログラムで
は、前記ＲＡＭのデータを使用して処理を実行す
ることを特徴とするエレベータの制御装置。 ２ 実用新案登録請求の範囲第１項において、 前記デユアルポートＲＡＭから前記ＲＡＭに転
送する際、前記データの異常を検出する異常検出
手段と、前記異常検出手段が動作したとき前記デ
ユアルポートＲＡＭから前記ＲＡＭへの転送を行
なわなくする手段、異常検出が所定回数以上連続
して起きたとき、前記エレベータの制御を規制す
る手段を備えたことを特徴とするエレベータの制
御装置。[Claims for Utility Model Registration] 1. Functions are shared by multiple microcontrollers, and dual port RA is used for data communication between the microcontrollers.
In an elevator using M, each microcomputer is provided with a RAM, and data in the dual port RAM is transferred to the RAM at each execution cycle of an elevator control program, and data in the RAM is transferred to the dual port RAM. An elevator control device, wherein the elevator control program executes processing using data in the RAM. 2. Utility Model Registration Claim 1 provides: abnormality detection means for detecting an abnormality in the data when the data is transferred from the dual port RAM to the RAM; and when the abnormality detection means operates, the data is transferred from the dual port RAM to the RAM. 1. An elevator control device comprising: means for preventing transfer to a RAM; and means for regulating control of the elevator when abnormality detection occurs a predetermined number or more consecutively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5654888U JPH01162474U (en) | 1988-04-28 | 1988-04-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5654888U JPH01162474U (en) | 1988-04-28 | 1988-04-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01162474U true JPH01162474U (en) | 1989-11-13 |
Family
ID=31282417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5654888U Pending JPH01162474U (en) | 1988-04-28 | 1988-04-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01162474U (en) |
-
1988
- 1988-04-28 JP JP5654888U patent/JPH01162474U/ja active Pending
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