JPH01162923U - - Google Patents
Info
- Publication number
- JPH01162923U JPH01162923U JP5896988U JP5896988U JPH01162923U JP H01162923 U JPH01162923 U JP H01162923U JP 5896988 U JP5896988 U JP 5896988U JP 5896988 U JP5896988 U JP 5896988U JP H01162923 U JPH01162923 U JP H01162923U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- amplifier
- type transistor
- ended
- pnp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Description
第1図は本考案の概念を表したブロツク図、第
2図は本考案の詳細な実施例回路図、第3図は本
考案の他の実施例回路図を示す。また第4図は従
来方法のブロツク図で、第5図は第4図のブロツ
ク図の一例の増幅回路図を示す。
Q1〜Q32,Q51〜Q62…トランジスタ
、R1〜R20,R51〜R54…抵抗、Rf1
,Rf2,Rf3,Rs1,Rs2,Rs3,R
a,Rb…抵抗、CNF,CNF2,CNF3,
CB2,CB3…コンデンサ、RL…負荷、Am
p1,Amp2,Amp3…増幅回路、…第1
の増幅器、…第2の増幅器、SEPPIa,b
…シングルエンデツド・プツシユプル回路、SE
PP…シングルエンデツド・プツシユプル回路
。
FIG. 1 is a block diagram showing the concept of the present invention, FIG. 2 is a detailed circuit diagram of an embodiment of the invention, and FIG. 3 is a circuit diagram of another embodiment of the invention. 4 is a block diagram of a conventional method, and FIG. 5 is an amplification circuit diagram of an example of the block diagram of FIG. 4. Q1 to Q32 , Q51 to Q62 ...Transistor, R1 to R20 , R51 to R54 ...Resistor, Rf1
, Rf 2 , Rf 3 , Rs 1 , Rs 2 , Rs 3 , R
a, Rb...resistance, CNF, CNF 2 , CNF 3 ,
CB2 , CB3 ...Capacitor, RL...Load, Am
p 1 , Amp 2 , Amp 3 ... amplifier circuit, ... first
amplifier, ...second amplifier, SEPPIa,b
…Single-ended push-pull circuit, SE
PP...Single-ended push-pull circuit.
Claims (1)
動増幅器より構成する第1の増幅器と、 前記第1の増幅器の出力を増幅する上側がNP
N型、下側がPNP型のトランジスタより構成さ
れる、2つのシングルエンデツド・プツシユプル
回路をバランスド・トランスフオーマレス回路構
成してある第2の増幅器及び、 第2の増幅器の出力を増幅する上側がPNP型
、下側がNPN型のトランジスタ及びカレントミ
ラー回路をブリツジ構成したシングルエンデツド
・プツシユプル回路を備える事を特徴とする電力
増幅回路。[Claims for Utility Model Registration] A first amplifier consisting of a double-ended differential amplifier having an input terminal and a negative feedback terminal;
a second amplifier configured with two single-ended push-pull circuits configured as a balanced transferless circuit, each consisting of an N-type transistor and a PNP-type transistor on the lower side; A power amplifier circuit comprising a single-ended push-pull circuit in which the side is a PNP type, the lower side is an NPN type transistor, and a current mirror circuit is configured as a bridge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5896988U JPH0753299Y2 (en) | 1988-04-30 | 1988-04-30 | Power amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5896988U JPH0753299Y2 (en) | 1988-04-30 | 1988-04-30 | Power amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01162923U true JPH01162923U (en) | 1989-11-14 |
| JPH0753299Y2 JPH0753299Y2 (en) | 1995-12-06 |
Family
ID=31284760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5896988U Expired - Lifetime JPH0753299Y2 (en) | 1988-04-30 | 1988-04-30 | Power amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0753299Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017515404A (en) * | 2014-05-01 | 2017-06-08 | 日本テキサス・インスツルメンツ株式会社 | Current limiting in amplifier systems. |
-
1988
- 1988-04-30 JP JP5896988U patent/JPH0753299Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017515404A (en) * | 2014-05-01 | 2017-06-08 | 日本テキサス・インスツルメンツ株式会社 | Current limiting in amplifier systems. |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0753299Y2 (en) | 1995-12-06 |
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