JPH01173652A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize large capacitance and high integration density by a method wherein the channel length of a second transistor on the side of a source is made shorter than the channel length of a first transistor on the side of a drain. CONSTITUTION:A drain and a source of a NAND cell are connected to a bit line BL and a reference potential via a first and a second selective MOS transistors SD, SS, respectively; the channel length of the second selective MOS transistor SS on the side of the source is made shorter than the channel length of the first selective MOS transistor SD on the side of the drain. By this setup, the area of a memory cell can be reduced; an EEPROM of high density can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a nonvolatile semiconductor memory device using a rewritable memory cell having a floating gate and a control gate.

(Prior Art) In the field of EFROM, an ultraviolet erasable nonvolatile memory device using a memory cell having a MO8FET structure with a floating gate is widely known. Among EFROMs, those that can be electrically erased are known as E''FROMs.The memory array of this type of EFROM is constructed by arranging memory cells at each intersection of row lines and column lines that intersect with each other. In the actual pattern, the drains of the two memory cells are made common and the column lines are contacted here to minimize the cell occupation area.However, even with this,
A contact portion with a column line is required for each common drain of two memory cells, and this contact portion occupies a large portion of the cell occupation area.

On the other hand, recently, memory cells are connected in series and NAND
An EPROM has been proposed that has 111 cells and can greatly reduce the number of contact parts.The configuration of such a NAND cell is to use 5NAN transistors with the first selection MO8) transistor on the drain side of the NAND cell.
Generally, a second selection NOS transistor is arranged on the source side of the D cell and connected to the bit line and the ground potential.

(Problems to be Solved by the Invention) However, in order to increase capacity, even higher integration is desired.

An object of the present invention is to provide a nonvolatile semiconductor memory device that solves these problems.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides the first and second selection gate transistors of the NAND cell described above, in which the channel length of the second transistor on the source side is set to the channel length of the first transistor on the drain side. It is characterized by being shorter than the channel length.

(Function) In the present invention, since the channel length of the second transistor on the source side can be reduced, the area of the memory cell region can be reduced, and the chip area can be reduced.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

The NAND cells are arranged in a matrix as shown in FIG. Looking at one NAND cell along the bit line BL, the drain of the memory cell M at one end of the NAND cell is connected to the bit line BL via the selected transistor 8D.
1, and the source of the memory cell A/M4 at the other end is connected to the ground potential via the selection MOS transistor SS. The same applies to other bit lines. Control lines CG, , CG, , . . . which commonly connect the control gates of memory cells in a direction perpendicular to the bit lines are word lines WL,
, WL, , . . . are arranged together. Adjacent NAND cells across 7 tacts in the pit line direction, the blocks have common rows, and output lines RD1 to RD4 from the decoder.
is installed. In addition, block selection lines SD1, SD
2 are arranged. These are turned on and off by PRO. FIG. 1(a) is a cross-sectional view of one NAND cell taken in the channel direction. Each memory cell has a source and a drain on the P-type Si substrate 1? The mold layer 2 is shared by adjacent ones, and a floating gate 3 and a control gate 4 are stacked in a self-aligned FAMO8 structure using a two-layer polycrystalline silicon film.

That is, a floating gate 3 is formed on a substrate 1 with a first gate insulating film made of a thermal oxide film interposed therebetween, and a control gate 4 is formed thereon with a second gate insulating film interposed therebetween. FIG. 1(b) is a cross-sectional view of the memory cell section viewed in a direction perpendicular to the channel direction, and the floating gate 3 is extended even onto the element isolation region. As a result, the coupling capacitance between the floating gate 3 and the control gate 4 is set larger than the coupling capacitance between the floating gate 3 and the substrate 1, and writing is performed only by exchanging electrons due to the tunnel effect between the floating gate 3 and the substrate 1. It is now possible to disappear.

Further, a selection gate SS%SD is formed by the first layer and the second layer polycrystalline silicon film. This selection game) 88S
The first and second layer polycrystalline silicon films of 8D are connected by through holes (not shown) at predetermined intervals in the direction in which they are disposed. The first gauge insulating film in the memory cell portion is a thermal oxide film with a thickness of 100 A, and the first gate insulating film in the selection gate portion 88°8D is a thermal oxide film with a thickness of 400 A. On the other hand, the second gate insulating film of the memory cell portion, the selection gate portion 88. The second gate insulating film of the SD is a silicon oxide film/silicon nitride film/silicon oxide film, each having a thickness of 250 Å, that is, an OMO structure. Erasing operation is performed by setting the Bit line potential (Vp) and source potential Vs to a low potential (0■).
, select transistor SD gate) SDI, 8D2 to HI
+ level, by setting word m (WLi to WL4) to H" level, electrons are tunneled and injected into the floating gate from the substrate side via the gate insulating film 3. 'H'° level is, for example, 20V.

The substrate potential was set to 0. 881 and 882 are 0. The write operation is sequentially performed starting from the memory cell farther from the contact with the bit line, that is, the memory cell closer to the source. From cell M4 to M3. Write Ml and Ml sequentially.

First, writing to the memory cell /l/Ma is performed by setting the drain of the selection transistor SD to Vp = ``H'' or L' level, the gate to 5DI = ``H'' level, 5D2 = ``L'' level,
Word line WL1. WL,,WL, ni”H”L/Be#
give. Gate SS1. SS2 is at L11 level, ie OV. The nH)l level is, for example, 20V.

At this time, Vp is the selection transistor SD.

It is transmitted through the channels of memory cells M, ,M, ,M to the drain region of memory cell M4. Word line WL connected to the gate of memory cell M4 is at “L” level = OV
Therefore, at this time, a large electric field is applied between the control gate and the substrate in the memory M4. Coupling capacitance C3 between floating gate 3 and substrate 1, coupling capacitance C3 between floating gate 3 and control gate 4'
Since MkCt is C1>Cs, the electrons in the floating gate 3 pass through the insulating film to the substrate 1 due to the tunnel effect.
is released. In memory cells M, , M, , M, such electron emission does not occur because a high voltage is similarly applied to the control gate and the substrate. As a result, the threshold value of the memory cell M4 becomes constant, and data writing is performed. Continue to set SDI, WL, and WL to H” level and SD2 to “L”.
Keep it level WL.

When set to “L” level, memory cell M3
Data writing is performed in . Hereinafter, similarly, Ml v
Write data to Ml. Source side gate SS
Since SS1 is off, the bit line and source will not be switched by SS1 even if M4 becomes negative due to writing and turns on. For read operation, SDI is set to H'" (=5V), that is, turned on, and SD2 is set to "L".
”(=OV), that is, off, word lines WL, ~WL,
sets the selected one to “0” = (OV) and forces the others to O
Set it to 5V. That is, when only WL is '0', memory cell M1 is selected, and when only WL4 is '0', memory cell M4 is selected. For example, WLi force (”
When memory cell M1 is selected by Q” -WL!=WLs
Since =WL4="1", memory cells M and M4 are in the on state. The memory cell M1 is off when the threshold is positive and on when the threshold is negative. The gate S81 is set to H11, that is, turned on, and the gate Ss2 is set to "L", that is, turned off. Therefore, depending on the write state, it is determined whether or not current flows through the cell or block. This causes the vp terminal to
1°2 or "0" is obtained.

The factor that determines the channel length of this selection game SD, 88 is the punch-through breakdown voltage.

1st Choice Game) The worst condition in which you have to consider SD punch-through occurs when the following occurs.

That is, this occurs in an unselected NAND cell (when unselected, the gate of the first selection gate SD becomes 0) during writing (when electrons are extracted from the floating gate). At this time, the drain (hy) line of the first selection gate (BL))
P I) (e.g. tlf2 ov), K) SD is O
V, the source (n+ diffusion layer 21) is OV, and a high voltage of Vpp is applied to the source and drain sides, so if the channel L is short, punch-through occurs. When the current that flows due to punch-through increases, the potential of the bit line decreases, causing malfunction. Therefore, the selection game)
SD requires a sufficiently long channel length to avoid punch-through.

On the other hand, in the second selection gate 88, there is no possibility that a high voltage is applied between the source and the drain to cause fear of punch-through during writing or erasing. - When erasing in bulk, Vpp (e.g. 20V) is applied to the control game) CG, ~CG,
SD and Ss games) SDI, 8D2,881. S.S.
2 is also applied with a potential of Vp[) and a loading gate I is injected, but the source and drain of the second selection gate SS are at OV, which does not provide a condition for punch-through to occur. Writing to the floating gate 34 At this time, the second selection gate source side ON diffusion layer is Vss70
Although the potential increases slightly after writing, the potential difference is not large enough to cause punch-through between the two select gates and drains of the second select gate.Therefore, the channel length of the 20th select gate is miniaturized. becomes possible.

In this embodiment, the channel length of the first selection game (SD) is set to 1.
8μ, and the channel length of the second selection gate SS was 1.0μ.

〔Effect of the invention〕

As described above, according to the present invention, the channel length of the second selection gate on the ground side of the NAND circuit can be made as short as the channel length of the first selection gate on the bit line side. The area of the memory cell can be reduced and a high density EEFROM can be provided.

In FIG.
FIG. 2, a cross-sectional view showing the structure of a ROM, is a diagram showing the structure of an array of memory cells.

l... silicon substrate, 2, ~2. ... n medium layer, 3, ~ 34 ... floating gate, 4 ... control gate 1 M (M,, M,, ...) ... memory 7-channel BL (B
Ll, BL! ...) bit line, W L (W Ls,
W L, ,...)...word line, CG (C
G1. CG, , ・) ...control'! −) Terminal.

SD...first selection gate, SS...Second selection gate.

Agent: Patent Attorney Noriyuki Chika Same pine pine mountain light

Claims (2)

[Claims] (1) NAND cells in which floating gates and control gates are stacked on a semiconductor substrate and a plurality of rewritable memory cells are connected in series are arranged in a matrix, and the drains and sources of the NAND cells are arranged in a matrix, respectively. The second selection MOS transistor is connected to the bit line and the reference potential via the second selection MOS transistor, and the channel length of the second selection MOS transistor on the source side is shorter than the channel length of the first selection MOS transistor on the drain side. Non-volatile semiconductor memory device. (2) The nonvolatile semiconductor memory device according to claim 1, wherein writing is performed from the side farthest from the bit line.