JPH0117590B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a pattern indicating a difference in spectral level between signals of each channel and a composite value of spectral levels in a 2-channel stereophonic signal (hereinafter referred to as 2-channel signal). can be displayed movably on the screen of the display to visually confirm the presence of the audio signal, which is useful for adjusting the balance between two channel signals in audio equipment, adjusting various characteristics of the equipment, etc. This was made for the purpose of providing a signal level display device.

Monitoring the operating status of audio equipment, displaying its operating characteristics, and displaying various characteristics of input signals is essential for using audio equipment in optimal conditions. It is also well known that various display devices have been used in audio equipment since it is desirable from the standpoint of reproducing audio signals in good condition.

By the way, as a display device, the displayed content is visually clear.
It goes without saying that it is desirable that the displayed content be intuitively identifiable, and for this reason, attempts have been made to use special patterns as patterns to be displayed on the display surface of the display device. Ta.

As a display device configured to display a special pattern on the display surface of the display, for example, it is conceivable to configure the display device using a character generator; However, there are problems such as the number of patterns to be displayed is limited, the display cannot be performed in real time, and the pattern displayed on the display screen cannot be moved quickly and smoothly. It has not been possible to create a display device that can display a signal level in real time while the display position and size change depending on the signal level of an input signal by using a character generator.

Now, in order to form a good reproduction sound field using a stereo reproduction device using two channel signals, it is necessary to adjust the balance between each channel signal in the two channel signals. It is convenient to obtain good adjustment results if it is possible to visually check the balance between the two channel signals when adjusting the two channels. If a device is used that allows you to visually check the difference in the spectral level between the signals of each channel, you will not only be able to obtain better adjustment results, but also be able to visually check the difference in the spectral level between the signals of each channel. For example, a display device with such a configuration can be used for many purposes, such as being able to easily change the frequency component distribution of each channel signal of a two-channel signal from a given program source. It can be used effectively.

The present invention operates as an interface between a central control unit (CPU) and a memory that can store at least pattern data, display position, pattern type data, etc. Using a video signal generator capable of generating a composite video signal whose image content is determined by data and which complies with a predetermined specific standard method, the level of the spectrum of each channel signal of the two-channel signal is determined. An audio signal in which a quantitative change in difference is displayed in a specific pattern as a moving image, and a change in the composite value of the spectral level of each channel signal of two channels can be displayed as a change in the size of the pattern. The purpose of the present invention is to provide a signal level display device for audio signals that does not have the above-mentioned problems and can be effectively used for many purposes. The specific contents of the apparatus of the present invention will be explained in detail with reference to the drawings.

1 and 2 are block diagrams of different embodiments of a signal level display device for an audio signal according to the present invention, and in FIGS.
1 and 2 are input terminals for each channel signal of the 2-channel signal, and in the following explanation, input terminal 1 is the input terminal for the left channel (L channel) signal,
2 is an input terminal for a right channel (R channel) signal.

In addition, BAl and BAr are buffer amplifiers, BPFl ₁ ,
BPFl ₂ ...BPFrn, etc. are bandpass filters, and the subscripts l and r in the code indicating the bandpass filter are respectively bandpass filters.
indicates the distinction between those for the left channel and those for the right channel, and the subscripts 1, 2...n indicate that each bandpass filter has a different center frequency in their passband, and furthermore, for the right channel. The same subscript 1, 2 in the bandpass filter used and the bandpass filter used in the left channel.
The bandpass filters using n are assumed to have the same passband characteristics.

In the diagram, MPX is a multiplexer, CPU
is the central control unit, MM is the main memory, VDP is the video signal generator (video display processor), and VRAM is the video RAM (however,
RAM is random access memory), CRT is a display, and in the following explanation, the display is assumed to use a cathode ray tube.

Also, LA in Figure 1 and LAl ₁ ~ in Figure 2
LArn etc. are logarithmic amplifiers, and
ADC, and ADCL ₁ , ADCl ₂ ...ADCrn in Figure 2
are digital-to-analog converters, respectively.
3 to 5 in the figure are data buses.

The video signal generator VDP has a video RAM V.RAM connected to it via a data bus 4.
The image content is determined by various data stored in the video RAM and follows a predetermined standard method. This video signal generator VDP is configured to be able to generate a composite video signal, and is described in, for example, Nikkei McGraw-Hill's "Nikkei Electronics" March 30, 1981 issue (No. Texas Instruments' video display processor (VDP) introduced on pages 156 to 164)
In the following explanation, it is assumed that the video display processor described above is used as the video signal generating device VDP.

Figure 3 shows a video ram V.
FIG. 2 is a diagram showing an example of a memory map of RAM,
In the video RAM memory map shown in Figure 3, 1024 bytes from address 0 to 1023 are used as the sprite generator table (SGT), and 1024 bytes from address 1024 to 1791 are used as the sprite generator table (SGT).
768 bytes are used as the pattern name table (PNT), plus
128 bytes are used as the sprite attribute table (STA), 32 bytes from addresses 1920 to 1951 are used as the color table (CT), and 96 bytes from addresses 1952 to 2047 are unused. , from 2048 to 4015
2048 bytes are used as the pattern generator table (PGT).

The pattern generator table PGT is
For example, one specific pattern can be stored in 8 pixels x 8 pixels using 8 bytes each, so 8 x
It can store 256 types of patterns with 8 pixels.
The pattern information stored in this pattern generator table PGT is stored in the central controller
Although the pattern generator table PGT is transferred from the main memory MM in the initial state of the device by the operation of the CPU, it goes without saying that the pattern generator table PGT may be configured as a read-only memory (ROM).

As mentioned above, each 8-byte storage area in the pattern generator table PGT individually stores specific patterns of 8×8 pixels. To enable a specific pattern to be specified by a pattern name given to each storage area in which a specific pattern is stored. Pattern generator table PGT of the example shown in Figure 3
Now, 256 types of patterns can be specified using 256 pattern names from pattern name #1 to pattern name 255.

Next, the pattern name table PNT is used to store information indicating which pattern name in the pattern generator table PGT each of the display sections assumed on the display surface of the display CRT corresponds to. It has a storage capacity corresponding to the total number of displayed display sections.

In the example shown in Figure 4, the total number of sections set on the display screen is {(32 columns) x (24 rows)} = 768, and since 1 byte is used as the amount of information indicating one section, as described above. Pattern name table like PNT
is said to have a storage capacity of 768 bytes.

As mentioned above, the required number of patterns are stored in the pattern generator table PGT in the video RAM VRAM, and the required pattern names assigned to each pattern are as follows. Pattern name table PNT
When the video display processor VDP is stored in each section of the display screen,
Information stored in the pattern name table PNT in the video RAM VRAM described above,
Generates a composite video signal according to a specific standard format whose image content is defined by the information stored in the pattern generator table PGT and, if necessary, the information stored in the color table CT. A specific pattern is displayed on the display surface of the display CRT.

The discussion so far has focused on pattern generators and
The specific pattern stored in the table PGT is 768 on the display screen.
This relates to the case where a pattern is displayed in a display mode in which it is displayed in a specific section among the sections, a so-called graphic mode. Since the position of a pattern is specified by PNG, when an attempt is made to move one pattern on the display screen, the pitch of pattern movement is one section (distance of 8 pixels) on the display screen.

Therefore, in order to reduce the pitch of movement of the pattern on the display surface and make the pattern move smoothly, it is necessary to use the sprite generator table.
The pattern stored in the SGT is moved within the display screen by one pixel pitch by changing the coordinates.

The patterns stored in the sprite generator table SGT may be 8 pixel x 8 pixel sprite data or 16 pixel x 16 pixel sprite data.
Each pattern stored in the sprite generator table SGT is individually assigned a sprite name such as #0, #1...#N, but the sprite surface corresponding to the pattern with each sprite name is The smaller the numerical value indicated by the sprite name, the higher the priority.

In the memory map of the video RAM VRAM illustrated in FIG. 3, 1024 bytes from address 0 to address 1023 are assumed to be used as the sprite generator table SGT, as described above. In this example, if the pattern is 8 pixels x 8 pixels, 128 patterns (sprite names #0 to #127) can be stored, and if the pattern is 16 pixels x 16 pixels, 32 Patterns (sprite names #0 to #31) can be stored. In the video RAM VRAM, if 2048 bytes are allocated to the sprite generator table SGT, the number of patterns stored in the sprite generator table STG will be twice that of the previous case. Not even.

The sprite attribute table SAT uses 4 bytes for each sprite and contains the sprite's position (1 byte each for specifying vertical and horizontal positions), display sprite name (1 byte), color coat, and Since the end code (1 byte) of the display sprite is set, if 128 bytes are used as the sprite attribute table SAT, this sprite attribute table SAT has 32 bytes.
Information for sprites is stored.

The position of the sprite is determined by 256 pixels (8 pixels x 32 sections) in the horizontal direction (X direction) and 192 pixels (8 pixels x 24 sections) in the vertical direction (Y direction) on the display screen.
49152 The coordinates of the pixel, the vertical position (a number that indicates the number of pixels in the vertical direction), and the horizontal position (the number that indicates the number of pixels in the horizontal direction) are stored in the sprite attribute table. It is determined by writing to SAT (the base point of the sprite is set to the upper left corner of the sprite), and the movement of the sprite is 1
This can be done at pixel pitch.

In the audio signal level display device of the present invention, a plurality of types of patterns are stored in the sprite generator table SGT, and the pattern to be displayed on the display surface is selected and the mode of movement of the pattern is specified. etc. are performed using the data written in the sprite attribute table SAT corresponding to the signal level of the audio signal. The pattern is displayed in a movable manner so that the signal level is displayed on the display surface of the display in a pattern such as that shown in FIG. 5 or 6, for example. .

In Figures 5 and 6, the vertical axis is the frequency value,
The horizontal axis is the signal level Sr and L of the R channel signal.
It is said to indicate the logarithm value logSr/Sl of the ratio Sr/Sl to the signal level Sl of the signal of the R channel, and the center of the horizontal axis is the signal level Sr of the signal of the R channel and the signal level Sl of the signal of the L channel. It shows the position of the pattern when the are equal.

The display screen pattern shown in Fig. 5 is created by displaying vertical lines and frequency scales in the center of the horizontal axis of the display screen in the graphic mode described above, and then This is an example in which a specific pattern is displayed on the sprite surface at a position corresponding to the logarithmic value of the signal level ratio of signals in each specific band, and is also shown in FIG. The pattern on the display screen is to display vertical lines and frequency scales at the center of the horizontal axis of the display screen, horizontal lines at the center of the vertical axis of the display screen, etc. in the graphic mode described above, and then to display each of the two channels. At a position corresponding to the logarithmic value of the signal level ratio of the signals of each specific band in the channel signal, the magnitude changes according to the composite value of the signals of the same band in each channel signal of the two channels. This is an example of a case where a specific pattern is displayed on the sprite surface so that the pattern appears on the display surface.

The display of the signal level of the audio signal according to the pattern as illustrated in FIGS. 5 and 6 is similar to the signal level of the audio signal of the present invention as shown in FIGS. This can be easily done using a display device.

That is, the L channel signal of the 2-channel signal is given from the input terminal 1 via the buffer amplifier BAl to the bandpass filters BPFl ₁ to BPFln, thereby being band-divided into signals of specific frequency bands. The R channel signal is applied from the input terminal 2 to the bandpass filters BPFr ₁ to BPFrn via the buffer amplifier BAr, thereby being divided into signals of specific frequency bands.

In the embodiment shown in FIG. 1, the L channel signal and the R channel signal, which are band-divided by the bandpass filters BPFl ₁ to BPFln and BPFr ₁ to BPFrn, are sequentially switched by the multiplexer MPX. As a result, the signals are made into time-division signals aligned on the time axis and supplied to the logarithmic amplifier LA.
The signal is then converted into a digital signal by an analog-to-digital converter ADC, and is applied to the central control unit CPU. is applied to each analog-to-digital converter ADCl ₁ to ADCrn via a logarithmic amplifier LAl ₁ to LArn provided, and each of said analog-to-digital converters
The digital signals from ADCl ₁ to ADCrn are sequentially switched by the multiplexer MPX to form time-division signals aligned on the time axis and provided to the central control unit CPU.

Timing signals for switching operations in multiplexer MPX, analog-to-digital converter ADC,
Timing signals for AD conversion operations such as ADCl ₁ to ADCrn are supplied from the central control unit CPU to multiplexers, analog-to-digital converters, and the like.

The signal level display device having the configuration shown in FIG. 1 and the signal level display device having the configuration shown in FIG. 2 perform the following signal level display operation under the control of the central control unit CPU.

That is, first, when the device is powered on, system initialization is performed to clear the contents of the main memory MM, video RAM V, RAM, etc., and to clear the contents of the main memory MM, video RAM V, RAM _{, etc.} ADCrn) conversion output is also cleared. Next, the registers in the video display processor VDP are set, and the storage areas such as the video RAM VRAM are set for what table they are used for, and the operating mode is set. Next, from the read-only memory in the main memory MM to the pattern generator table PGT,
Predetermined types of pattern information (for example, pattern information such as vertical lines and frequency scales in the horizontal center of FIG. (pattern information such as horizontal lines in the center of Color data etc. are transferred.

Next, the required sprite pattern is transferred from the read-only memory in the main memory MM to the sprite generator table SGT, and the pattern name table PNT
The required data is transferred to

After the above operations are performed under the control of the central control unit CPU, the multiplexer MPX and analog-to-digital converter ADC (or ADCl ₁ ~ ADCrn) are activated by the timing signal from the central control unit CPU.
As a result of the predetermined operation of
The signal level value for each band of the channel and the corresponding digital data are respectively written into predetermined tables in the main memory MM.

The central control unit CPU inputs the L channel and R channel in the digital data respectively written in the predetermined tables in the main memory MM as described above.
Comparison calculations are performed for each band in the same band as the channel, and the calculation results are converted into position information in the X direction, which is then sent to the video display processor.
It is written as successive X-direction position data in the sprite attribute table in the video RAM VRAM via the VDP.

The video display processor uses the pattern information stored in the pattern generator table PGT and the pattern name table
Depending on the pattern name stored in PNT,
Generates a composite video signal capable of displaying vertical lines and frequency scales (and horizontal lines) on the back of the display screen and supplies it to the display CRT, as well as the sprite generator table.
The display is created using sprite pattern information stored in the SGT, position information and other information stored in the sprite attribute table.
A composite video signal capable of displaying a sprite pattern on the display screen of a CRT is generated and supplied to the display CRT.

As a result, on the display surface of the display CRT,
As shown in FIG. 5, a signal level is displayed using a specific sprite pattern for each position in the X direction corresponding to the logarithmic value of the ratio between signals in the same band of the L channel and the R channel.

The size of the sprite pattern displayed on the display surface of the display CRT can be changed by setting the L channel and R channel.
The display mode shown in Figure 6, in which the signal level is displayed on the display CRT by changing it according to the composite value of the signals in the same band as the channel, has already been used as a calculation performed by the central control unit CPU. In addition to the comparison operation described above, a synthesis operation is also performed on the digital data of the same band of the L channel and the R channel, and based on the result of the comparison operation described above, position information of the pattern in the X direction is generated. data (sprite names) indicating sprite patterns of different sizes are determined depending on the result of the composite operation,
This can be easily achieved by writing such data into the sprite/attribute table.

In addition, when implementing this, the repetition period of a series of conversion operations by the analog-to-digital converter should be the vertical scanning period, and the central control unit CPU
In a preferred embodiment, the transfer of data from the VRAM to the video RAM is performed by interrupt only during the horizontal blanking period and the vertical blanking period.

As is clear from the detailed explanation above, the audio signal signal level display device of the present invention displays the display screen by the logarithm of the ratio between the signals of the same band in each channel of the two-channel signal. Since the position of the inner pattern in the X direction is determined, the state of the difference in the signal level of the signal for each of the plurality of divided bands in each of the two channels can be immediately recognized visually. This makes it easy to adjust equipment and change signal characteristics, and also makes it possible to easily adjust the equipment and change the signal characteristics. By displaying the signal in a changed state depending on the composite value of the signals, it is possible to more easily adjust the equipment and change the signal characteristics.

[Brief explanation of drawings]

1 and 2 are block diagrams of different embodiments of the apparatus of the present invention, FIG. 3 is an example of a video RAM memory map, FIG. 4 is an explanatory diagram of the divisions of the display surface, and FIGS. FIG. 6 is an explanatory diagram of the displayed pattern. 1, 2...Input terminal, 3-5...Data bus,
BAl, BAr……Buffer amplifier, BPFl ₁ ~ BPFrn
... Bandpass filter, MPX ... Multiplexer,
LA, LAl ₁ ~ LArn...Logarithmic amplifier, CPU...Central control unit, VDP...Video display
Processor, MM...Main memory, V RAM
...video ram, CRT...display.

Claims (1)

[Scope of Claims] 1. Means for band-dividing the signals of each channel of the two-channel input signal, analog-to-digital conversion means for converting the output signal from the band-splitting means into a digital signal, and each of the above-mentioned devices. A central control unit that compares and calculates output signals from the analog-to-digital conversion means for signals in mutually corresponding bands in the channel signals, converts the result into position information and outputs it, and output data of the central control unit described above. a first memory area which is connected to the video display processor by bus and stores at least a predetermined pattern; and a coordinate position on the display surface. a second memory having a second memory area for storing data for specifying the central controller, and a second memory in the memory for transmitting the output data from the central controller through the video display processor; 2 above from the video display processor by writing to the
A signal level display device for an audio signal in which a pattern on a display surface of a display is displayed while being moved in the horizontal axis direction according to differences in signal level for each band of an input signal of a channel. 2. The pattern displayed on the display surface of the display has a shape according to the data stored in the first memory area of the memory, and also has a shape according to the coordinate data stored in the second memory area of the memory. 2. The signal level display device for an audio signal according to claim 1, wherein the timing of generation of the signal level is specified. 3. The signal level display device for an audio signal according to claim 1, wherein the signal conversion period in the analog-to-digital conversion means is synchronized with the vertical scanning period. 4 Means for band-dividing the signals of each channel of the two-channel input signal, digital-to-analog converting means for converting the output signal from the band dividing means into a digital signal, and mutual correspondence in the signals of the respective channels. The output signals from the analog-to-digital conversion means are compared and calculated for the signals in the respective bands, and the results are converted into position information and outputted. a central control unit that performs a composite calculation on the signal level of the output signal from the digital conversion means, converts the result into pattern information, and outputs it; a video display processor to which the output data of the central control unit is applied; A first memory area that is connected to the video display processor by bus and stores at least a predetermined pattern, and a second memory area that stores data for specifying coordinate positions on the display surface. 2 channels from the video display processor by writing the output data from the central controller to the memory via the video display processor. The pattern on the display surface is moved in the horizontal axis direction according to the difference in signal level for each band of the input signal of the 2-channel input signal, and the size of the pattern is changed according to the composite value of the signal level for each band of the 2-channel input signal. A signal level display device for an audio signal in which a pattern of states in which the intensity changes is displayed on a display screen. 5. The pattern displayed on the display surface of the display has a shape according to the data stored in the first memory area of the memory, and also has a shape according to the coordinate data stored in the second memory area of the memory. 5. The signal level display device for an audio signal according to claim 4, wherein the timing of generation of the signal level is specified. 6. The signal level display device for audio signals according to claim 4, wherein the signal conversion period in the analog-to-digital conversion means is synchronized with the vertical scanning period.