JPH0117871Y2 - - Google Patents
Info
- Publication number
- JPH0117871Y2 JPH0117871Y2 JP1983036731U JP3673183U JPH0117871Y2 JP H0117871 Y2 JPH0117871 Y2 JP H0117871Y2 JP 1983036731 U JP1983036731 U JP 1983036731U JP 3673183 U JP3673183 U JP 3673183U JP H0117871 Y2 JPH0117871 Y2 JP H0117871Y2
- Authority
- JP
- Japan
- Prior art keywords
- output
- switch
- threshold
- circuit
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Transmitters (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は出力電力制御回路を有するSSB送信機
のキヤリアサプレツシヨンの改善に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an improvement in carrier suppression of an SSB transmitter having an output power control circuit.
SSB通信は専有周波帯域幅が狭く、電力増幅段
の電力効率が良いことから、特に長距離通信に適
しており、従つて送信機出力電力を少なくとも
10W以上であるのが普通である。しかし最近は
SSB方式の普及により短距離の通信にも利用され
ることが多く、その場合には混信妨害防止の見地
から出力を例えば1W以下に低減して使用するこ
とが望ましく、その目的のため電力低減スイツチ
を備えた送信機が多くなつている。
SSB communication is particularly suitable for long-distance communication due to its narrow proprietary frequency bandwidth and the high power efficiency of the power amplification stage, thus reducing the transmitter output power to at least
Usually it is 10W or more. But recently
With the spread of the SSB method, it is often used for short-distance communication, and in that case, it is desirable to reduce the output to, for example, 1W or less to prevent interference, and for that purpose, a power reduction switch is used. There are an increasing number of transmitters equipped with
SSB送信機で出力を低減する最も簡単な手段は
変調入力を低減する方法であるが、これは変調度
を浅くしてサンドバンド電力を低下するのである
から、SSB発生段におけるキヤリア洩れの程度を
示すキヤリアサプレツシヨンが悪化するのと、残
留雑音によるS/Nの低下となるので、望ましい
方法ではない。
The simplest way to reduce the output of an SSB transmitter is to reduce the modulation input, but since this reduces the modulation depth and reduces the sandband power, it reduces the degree of carrier leakage in the SSB generation stage. This is not a desirable method because it worsens the carrier suppression shown and reduces the S/N ratio due to residual noise.
そのため、従来の多くの機器においては、送信
機の出力電力のレベルを検出して、SSB発生段と
出力増幅段の中間の、いわゆる前段部に帰還して
前段部のゲインを制御することにより、出力電力
のレベルを設定する方法が用いられている。この
場合は、SSB発生段の出力までの動作は同様であ
るし、前段部のゲインを制御することにより、出
力電力のレベルを設定する方法が用いられてい
る。この場合はSSB発生段の出力までの動作も同
様であるし、前段部のゲインを低下して出力を低
減するものであるから、キヤリアサプレツシヨン
もS/Nも悪化しないわけである。しかしなが
ら、送話の途切れた時点では前段部のゲインは制
御されず、フルゲインとなるため、キヤリアサプ
レツシヨンの悪化とS/Nの低下が目立つ心配が
ある。本考案はこのような点の解決のために行な
われたものでキヤリアサプレツシヨンもS/Nも
悪化しない送信出力低減回路の提供を目的とす
る。 Therefore, in many conventional devices, the output power level of the transmitter is detected and fed back to the so-called pre-stage section, which is between the SSB generation stage and the output amplification stage, and the gain of the pre-stage section is controlled. A method of setting the level of output power is used. In this case, the operation up to the output of the SSB generation stage is the same, and a method is used in which the output power level is set by controlling the gain of the front stage. In this case, the operation up to the output of the SSB generation stage is the same, and the output is reduced by lowering the gain of the front stage, so neither carrier suppression nor S/N deteriorates. However, at the point when the transmission is interrupted, the gain of the front stage is not controlled and is at full gain, so there is a concern that the carrier suppression will deteriorate and the S/N ratio will be noticeably lowered. The present invention was developed to solve these problems, and aims to provide a transmission output reduction circuit that does not deteriorate carrier suppression or S/N ratio.
出力電力の一部を出力分割器で取り出し、検出
器で整流検出し、該検出器にはしきい値電圧を逆
バイアスで加えて検出値を制御する。この検出出
力は前段増幅器に帰還されて出力電力を制限され
る。さらにSSB信号発生器と前段増幅器の間に信
号減衰量設定回路とスルー回路を並設し、第1の
スイツチで選択切換える。この第1のスイツチと
しきい値設定の第2スイツチは連動する機構であ
り、信号減衰量設定回路の選択と帰還量が大のし
きい値との設定が対応するよう構成されている。
A part of the output power is taken out by an output divider, rectified and detected by a detector, and a threshold voltage is applied to the detector with a reverse bias to control the detected value. This detection output is fed back to the preamplifier to limit the output power. Furthermore, a signal attenuation amount setting circuit and a through circuit are installed in parallel between the SSB signal generator and the preamplifier, and the selection is made by a first switch. The first switch and the second threshold setting switch are interlocking mechanisms, and are configured so that the selection of the signal attenuation amount setting circuit corresponds to the setting of the threshold value with a large feedback amount.
本考案を図面について説明する。1はSSB信号
発生器であつて、通常平衡変調器および片サイド
バンド除去フイルタによりSSB信号を作つてい
る。2は前段増幅器(ドライバー段ともいう)で
あつて、SSB信号を、出力(電力ともいう)増幅
段3をドライブするに必要なゲインを持ち、出力
制御電圧が加わる分だけゲインが低下するように
動作する。
The present invention will be explained with reference to the drawings. Reference numeral 1 denotes an SSB signal generator, which normally generates an SSB signal using a balanced modulator and a sideband removal filter. 2 is a pre-stage amplifier (also called a driver stage), which has the gain necessary to drive the SSB signal to the output (also called power) amplification stage 3, and has a gain that is reduced by the amount of output control voltage added. Operate.
出力電力はアンテナ4に送出すると同時にその
一部を出力分割器5を通して取り出し、検出器6
で整流して直流の制御電圧61となり、前段増幅
器2に帰還してゲインを制御している。この制御
動作は検出器6の動作開始のしきい値を加減する
ことにより制御の深さを調節でき、しきい値を低
くするほど制御動作は深く、しきい値を高くする
ほど制御動作は浅くなり、制御を停止することも
できる。このしきい値の設定は検出器6に加える
逆バイアス電圧を加減するのが簡単である。図で
は検出器6と直列に抵抗10を入れ、電源回路等
のなるべく一定電位の回路より抵抗11または抵
抗12を通して電流を流し、抵抗10の両端に逆
バイアス電圧を発生させている。抵抗10は一定
であるから、直流抵抗11,12は抵抗値が小さ
いほど逆バイアス電圧は大きくなるから、しきい
値設定スイツチ7で抵抗11と12を切換えて希
望の出力電圧レベルとなるように抵抗値を設定す
ればよい。さらに、本考案ではしきい値設定第2
のスイツチ7と機構的に連動して動作する第1の
スイツチ9A,9Bはスルー回路と信号減衰量設
定器8との切換えスイツチであり、信号減衰量設
定器8はSSB信号発生器1と前属増幅器2の間に
設けてあり、SSB信号に変換後の減衰回路である
ので、減衰にともなう悪影響はない。この第1ス
イツチ9A,9Bとしきい値設定の第2スイツチ
7の連動条件はしきい値設定の第2スイツチ7が
最大バイアス電圧を設定して帰還電圧61が最小
値のときは第1スイツチ9A,9Bはスルー回路
側であり第1スイツチ9A,9B間での減衰は行
わない。しきい値設定の第2スイツチがしきい値
電圧の小さい方を選択する制御電圧61が最大値
となつて前段増幅器の増幅度を下げると共に第1
スイツチ9A,9Bが信号減衰量設定器に切り換
わり、前段増幅器2の入力も低下させ低出力送信
時の安定した出力低減により、無変調または低変
調期間におけるキヤリアサプレツシヨンおよび
S/Nの低下を防止する。なお前段部の信号減衰
量設定器8は図示のSSB発生器1と前属増幅器2
の中間に限定されることなく、前段増幅器2と出
力増幅段3の中間に入れてもよく、前段増幅器2
の段間に設けることもあり、設計上自由の範囲に
属するものである。 The output power is sent to the antenna 4 and at the same time a part of it is taken out through the output divider 5 and sent to the detector 6.
The voltage is rectified to become a DC control voltage 61, which is fed back to the preamplifier 2 to control the gain. The depth of this control operation can be adjusted by adjusting the threshold for starting the operation of the detector 6; the lower the threshold, the deeper the control operation, and the higher the threshold, the shallower the control operation. It is also possible to stop the control. This threshold value can be easily set by adjusting the reverse bias voltage applied to the detector 6. In the figure, a resistor 10 is inserted in series with the detector 6, and a current is passed through the resistor 11 or 12 from a circuit with a constant potential, such as a power supply circuit, to generate a reverse bias voltage across the resistor 10. Since the resistor 10 is constant, the smaller the resistance value of the DC resistors 11 and 12, the greater the reverse bias voltage. Therefore, the threshold setting switch 7 switches the resistors 11 and 12 to obtain the desired output voltage level. Just set the resistance value. Furthermore, in this invention, the second threshold setting
The first switches 9A and 9B, which operate mechanically in conjunction with the switch 7, are switches between the through circuit and the signal attenuation setting device 8 , and the signal attenuation setting device 8 is connected to the SSB signal generator 1 and the front. Since the attenuation circuit is provided between the main amplifiers 2 and is an attenuation circuit after conversion to an SSB signal, there is no adverse effect due to attenuation. The interlocking condition of the first switches 9A, 9B and the second switch 7 for setting the threshold value is that when the second switch 7 for setting the threshold value sets the maximum bias voltage and the feedback voltage 61 is the minimum value, the first switch 9A , 9B are on the through circuit side, and no attenuation is performed between the first switches 9A and 9B. The second switch for threshold setting selects the smaller threshold voltage.The control voltage 61 reaches its maximum value, lowering the amplification of the front stage amplifier and
Switches 9A and 9B are switched to signal attenuation setting devices, and the input to the preamplifier 2 is also lowered, resulting in stable output reduction during low output transmission, resulting in carrier suppression and S/N reduction during no modulation or low modulation periods. prevent. The signal attenuation setting device 8 in the previous stage is connected to the SSB generator 1 and the previous amplifier 2 shown in the figure.
It may be placed between the pre-stage amplifier 2 and the output amplification stage 3, and the pre-stage amplifier 2
It is sometimes provided between stages, and is within the scope of design freedom.
本考案による低減回路を連動して入力側及び出
力側の両方で行うことにより、キヤリアサプレツ
シヨンもS/Nの低下もなく最良状態で出力を低
減できるので、実用上の効果は大きい。
By interlocking the reduction circuit according to the present invention on both the input side and the output side, the output can be reduced in the best condition without carrier suppression or S/N deterioration, which has a great practical effect.
図は本考案の一実施例のSSB送信機の出力制限
回路のブロツク図である。
1……SSB信号発生器、2……前段増幅器、3
……出力増幅段、5……出力分割器、6……検出
器、7……しきい値設定スイツチ、8……信号減
衰量設定器。
The figure is a block diagram of an output limiting circuit of an SSB transmitter according to an embodiment of the present invention. 1...SSB signal generator, 2...Pre-stage amplifier, 3
... Output amplification stage, 5 ... Output divider, 6 ... Detector, 7 ... Threshold setting switch, 8 ... Signal attenuation amount setting device.
Claims (1)
中線を縦続結線し、前記出力増幅器の出力側にコ
ンデンサよりなる出力分割器を接続して出力電力
レベルを検出し、前記前段増幅器に帰還して前段
増幅器のゲインを制御することにより出力電力の
レベルを設定する送信機または送受信機の送信部
において、前記SSB信号発生器と前記前段増幅器
の間にスルー回路と抵抗による信号減衰量設定器
を並設して第1のスイツチで選択切換える手段
と、前記出力分割器の出力側に負電圧を出力する
検波用ダイオードと、コイルを介して抵抗とコン
デンサで並列接地し、前記コイルと前記抵抗の接
点に帰還量を設定する二つのしきい値電圧を第2
のスイツチで切換え入力する手段とを具備し、該
第2のスイツチと前記第1のスイツチは連動し、
前記第1のスイツチがスルー回路を選択すると前
記第2のスイツチは帰還量が小のしきい値側であ
り、前記第1のスイツチが信号減衰設定器側では
前記第2のスイツチは帰還量が大のしきい値を選
択することを特徴とする送信機の回路。 An SSB signal generator, a pre-stage amplifier, an output amplifier, and an antenna are connected in cascade, and an output divider made of a capacitor is connected to the output side of the output amplifier to detect the output power level, and the output power level is returned to the pre-stage amplifier. In a transmitting section of a transmitter or transceiver that sets the level of output power by controlling the gain of the transmitter, a signal attenuation amount setting device using a through circuit and a resistor is installed in parallel between the SSB signal generator and the pre-stage amplifier. a detection diode that outputs a negative voltage to the output side of the output divider, a resistor and a capacitor that are grounded in parallel through a coil, and fed back to the contact point between the coil and the resistor. Set the two threshold voltages to the second
means for inputting switching with a switch, the second switch and the first switch are interlocked;
When the first switch selects the through circuit, the second switch is on the threshold side with a small feedback amount, and when the first switch is on the signal attenuation setting device side, the second switch is on the threshold side with a small feedback amount. A transmitter circuit characterized in that it selects a large threshold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3673183U JPS59154941U (en) | 1983-03-14 | 1983-03-14 | transmitter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3673183U JPS59154941U (en) | 1983-03-14 | 1983-03-14 | transmitter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59154941U JPS59154941U (en) | 1984-10-17 |
| JPH0117871Y2 true JPH0117871Y2 (en) | 1989-05-24 |
Family
ID=30167396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3673183U Granted JPS59154941U (en) | 1983-03-14 | 1983-03-14 | transmitter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59154941U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023112651A1 (en) * | 2021-12-16 | 2023-06-22 | 株式会社村田製作所 | High-frequency module and signal amplification method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5293209A (en) * | 1976-02-02 | 1977-08-05 | Hitachi Denshi Ltd | Control system of sending power |
| JPS616667Y2 (en) * | 1980-07-24 | 1986-02-28 |
-
1983
- 1983-03-14 JP JP3673183U patent/JPS59154941U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59154941U (en) | 1984-10-17 |
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