JPH01181547A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01181547A
JPH01181547A JP63004107A JP410788A JPH01181547A JP H01181547 A JPH01181547 A JP H01181547A JP 63004107 A JP63004107 A JP 63004107A JP 410788 A JP410788 A JP 410788A JP H01181547 A JPH01181547 A JP H01181547A
Authority
JP
Japan
Prior art keywords
pad
semiconductor device
high melting
point metal
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63004107A
Other languages
Japanese (ja)
Inventor
Norio Kususe
楠瀬　典男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63004107A priority Critical patent/JPH01181547A/en
Publication of JPH01181547A publication Critical patent/JPH01181547A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To avoid corrosion of a pad formed on a semiconductor substrate with an insulating film applied between the pad and the substrate, by covering the pad with a high melting-point metal or high melting-point metal silicide. CONSTITUTION:On a semiconductor substrate 1, a wiring layer 3 made of aluminum and a pad 4 are formed with a silicon oxide film 2 applied between the substrate and the wiring layer 3 and pad 4. On the wiring layer 3 and around the pad 4, a silicon nitride film 5 is formed as a passivation film. Especially on the surface of the pad 4, a self-aligned titanium.platinum layer 7 is formed. Therefore, even when this device is incorporated in a plastic-molded type package, the pad 4 is protected by the titanium.platinum layer, and thereby it is kept from corrosion.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に樹脂封止型パッケージ
を用いる半導体装置のパッドの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to the structure of a pad of a semiconductor device using a resin-sealed package.

〔従来の技術〕[Conventional technology]

従来の半導体装置のパッド部は一般に第２図に示すよう
に構成されていた。すなわち、拡散層等により半導体素
子が形成された半導体基板１の上に酸化硅素膜２を介し
てアルミニウムからなる配線層３及びパッド４を形成し
、パッシベーション膜として全面に窒化硅素膜５を形成
してパッド４上に窓を形成した構造である。The pad portion of a conventional semiconductor device was generally constructed as shown in FIG. That is, a wiring layer 3 and a pad 4 made of aluminum are formed via a silicon oxide film 2 on a semiconductor substrate 1 on which a semiconductor element is formed by a diffusion layer, etc., and a silicon nitride film 5 is formed on the entire surface as a passivation film. This structure has a window formed on the pad 4.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置を樹脂封止型パッケージに組
込む場合、リードフレーム端やボンディング線に沿って
侵入する水分と、封止樹脂材質の不純物、特に塩素によ
ってアルミニウム配線の腐食が引起こされる。周知のよ
うに半導体装置は、窒化硅素膜等のパッシベーション膜
で保護されているが、所謂ポンディングパッド部分のア
ルミニウムは保護されていないため腐食が進行すること
になり、ついにはパッド部のアルミニウムが無くなり、
端子のオープン不良となる品質に係わる欠点を持ってい
た。When the conventional semiconductor device described above is assembled into a resin-sealed package, corrosion of the aluminum wiring is caused by moisture that enters along the edges of the lead frame and bonding lines, and impurities in the sealing resin material, especially chlorine. As is well known, semiconductor devices are protected by a passivation film such as a silicon nitride film, but since the aluminum in the so-called bonding pad is not protected, corrosion progresses, and eventually the aluminum in the pad is damaged. Gone,
It had a quality-related defect that caused the terminal to open.

本発明の目的は、パッド部が腐食することのない高品質
の半導体装置を提供することにある。An object of the present invention is to provide a high quality semiconductor device in which the pad portion is not corroded.

Ｃ問題点を解決するための手段〕 本発明の半導体装置は、半導体基板上に絶縁膜を介して
形成されたパッドと該パッドの周囲を覆う保護膜とを有
する半導体装置であって、前記パッドは自己整合的に形
成された高融点金属層または高融点金属シリサイド層で
覆われているものである。Means for Solving Problem C] The semiconductor device of the present invention is a semiconductor device having a pad formed on a semiconductor substrate via an insulating film and a protective film covering the periphery of the pad. is covered with a high melting point metal layer or a high melting point metal silicide layer formed in a self-aligned manner.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

第１図において、半導体素子が形成された半導体基板１
上には、酸化硅素膜２を介してアルミニウムからなる配
線層３及びパッド４が形成されており、この配線Ｍ３上
及びパッド４の周囲にパッシベーション膜として窒化硅
素膜５が形成されている。そして、特にこのパッド４の
表面には自己整合的に厚さ約３０００人のチタン・白金
層７が形成されている。In FIG. 1, a semiconductor substrate 1 on which a semiconductor element is formed
A wiring layer 3 made of aluminum and a pad 4 are formed thereon via a silicon oxide film 2, and a silicon nitride film 5 is formed as a passivation film on the wiring M3 and around the pad 4. Particularly, on the surface of this pad 4, a titanium/platinum layer 7 having a thickness of approximately 3000 layers is formed in a self-aligned manner.

このように構成された本実施例においては、パッド４上
にチタン・白金層７が形成されているため、樹脂封止型
パッケージに組込んだ場合でも、パッド４はチタン・白
金Ｍ７に保護されるため、パッド４に腐食が生じること
は極めて少なくなる。In this embodiment configured as described above, since the titanium/platinum layer 7 is formed on the pad 4, the pad 4 is protected by the titanium/platinum M7 even when incorporated into a resin-sealed package. Therefore, occurrence of corrosion on the pad 4 is extremely reduced.

チタン・白金層７は、パッド４上に開口部を有するフォ
トレジスト膜を形成し、全面にチタン・白金層を蒸着法
等により形成したのち、フォトレジスト膜を除去するリ
フトオフ法により形成できる。The titanium/platinum layer 7 can be formed by a lift-off method in which a photoresist film having an opening is formed on the pad 4, a titanium/platinum layer is formed on the entire surface by a vapor deposition method, and then the photoresist film is removed.

尚、チタン・白金の代りにＷやＭｏ等の他の高融点金属
やそのシリサイドを用いてもよい。例えば、パッシベー
ション膜として全面に窒化硅素膜５を被着し、パッド４
上に窓を形成したのち、選択ＣＶＤ法によりパッド４上
にのみタングステンシリサイドを堆積する方法を用いる
ことができる。Note that other high melting point metals such as W and Mo or their silicides may be used instead of titanium or platinum. For example, a silicon nitride film 5 is deposited on the entire surface as a passivation film, and the pad 4 is
A method may be used in which a window is formed thereover and then tungsten silicide is deposited only on the pad 4 by selective CVD.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体基板上に絶縁膜を
介して形成されたパッドを高融点金属もしくは高融点金
属シリサイドで覆うことにより、従来のアルミニウムの
みのパッドに比べ腐食されることが極めて少なくなるた
め、半導体装置の信頼性は向上したものとなる。As explained above, the present invention covers a pad formed on a semiconductor substrate via an insulating film with a high melting point metal or a high melting point metal silicide, so that it is much less likely to be corroded than a conventional pad made only of aluminum. The reliability of the semiconductor device is improved because of the reduced amount.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の断面図、第２図は従来の半
導体装置の断面図である。 １・・・半導体基板、２・・・酸化硅素膜、３・・・配
線層、４・・・パッド、５・・・窒化硅素膜、７・・・
チタン・白金層。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Silicon oxide film, 3... Wiring layer, 4... Pad, 5... Silicon nitride film, 7...
Titanium/platinum layer.

Claims (1)

【特許請求の範囲】[Claims] 　半導体基板上に絶縁膜を介して形成されたパッドと該
パッドの周囲を覆う保護膜とを有する半導体装置におい
て、前記パッドは自己整合的に形成された高融点金属層
または高融点金属シリサイド層で覆われていることを特
徴とする半導体装置。In a semiconductor device having a pad formed on a semiconductor substrate via an insulating film and a protective film surrounding the pad, the pad is a high melting point metal layer or a high melting point metal silicide layer formed in a self-aligned manner. A semiconductor device characterized by being covered.
JP63004107A 1988-01-11 1988-01-11 Semiconductor device Pending JPH01181547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63004107A JPH01181547A (en) 1988-01-11 1988-01-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63004107A JPH01181547A (en) 1988-01-11 1988-01-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01181547A true JPH01181547A (en) 1989-07-19

Family

ID=11575570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63004107A Pending JPH01181547A (en) 1988-01-11 1988-01-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01181547A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006203215A (en) * 2006-01-23 2006-08-03 Renesas Technology Corp Semiconductor integrated circuit device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006203215A (en) * 2006-01-23 2006-08-03 Renesas Technology Corp Semiconductor integrated circuit device and manufacturing method thereof

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