JPH01183291A - Time switch circuit - Google Patents

Abstract

PURPOSE:To shorten the delay time of a signal and to reduce the scale of a circuit by providing a write address generating means to generate a write address to make the phases of respective multiframe coincide by using the output of a multiframe phase detecting means. CONSTITUTION:The write address is generated by the write address generating means 5 by using the output of the multiframe phase detecting means 3, and an input signal is written in a storing means 4 so that the phases of the multiframe coincide with each other. Because the replacement of a multiframe position is executed at the time when the signal written from the storing means 4 is read, if control to make the phases of the multiframe coincide is executed at the time of write, the both can be executed simultaneously without competition. Thus, the delay time of the signal is shortened, and simultaneously, the scale of the circuit is reduced.

Description

Detailed Description of the Invention [Summary] This invention relates to a time switch circuit used in a multimedia multi-M conversion device that time-division multiplexes, for example, 0 image signals, facsimile signals, audio signals, etc.
For the purpose of reducing the circuit scale, each time slot forms a multi-frame, and each multi-frame is composed of n-frame signals, but if the nine phases are in an undefined state for each time slot, the signal within the n-frame In a time switch circuit for exchanging frame positions, each multiframe is stored in a storage means using a multiframe phase 46 output means for detecting the phase of each multiframe and an output of the multiframe phase detection means. A write address generating means generates a write address such that the phases of each multi-frame match when writing, and a signal of a multi-frame configuration is written corresponding to the output of the write address generating means, and a read address to be input. and storage means from which the signal written in correspondence with the signal is read out.

[Industrial application field]

The present invention applies to image signals and facsimile signals, for example.

This invention relates to a time switch circuit used in a multimedia multiplex converter that time-division multiplexes audio signals and the like.

In recent years, there has been a trend to time-division multiplex not only data but also image signals, facsimile + J signals, etc., and transmit the same to the other party.

At this time, it is necessary to reduce the signal delay time in order to increase transmission efficiency and to reduce the circuit scale to make the device smaller.

[Conventional technology]

FIG. 3 is a block diagram of a conventional example, FIG. 4 is a multi-frame configuration diagram, and FIG. 5 is an explanatory diagram of the frame aligner operation in FIG. 4.

First, in FIG. 4, for example, the time of 125 μs is
As shown in Figure (a), n time slots (hereinafter referred to as n time slots).

(abbreviated as TS), and each TS consists of one frame synchronization focus F, data D1 to D1 as shown in FIG.
Assume that one multiframe is composed of 20 frames assembled using D, , and S bits.

Note that a frame synchronization pattern is formed by frame synchronization bits p+""Fto.

Here, as shown in Fig. 4(b), for TS 1, the frame synchronization pitch starts from F, (hereinafter abbreviated as +Fl) and ends at F2°, but for TS 2, it starts from F. and passes through F2° + FI and ends at F4,
F for TS3, ~F...F for TSn
□. ~F.

It is assumed that the phase of each multiframe is in an undefined state, as shown in the following.

Next, the operation shown in FIG. 3 will be explained with reference to FIG. When a signal having the configuration shown in (a) is manually generated, it is easy to detect how much phase delay the frame synchronization pattern in this signal has with respect to the built-in standard frame synchronization pattern.

For example, if the first frame synchronization bit of the multi-frame of TS 1 is F, and the phase matches the built-in standard frame synchronization pattern as F,, F, etc., as shown in Figure 5 (
As shown in a), write addresses 1, 2, . . . 20 are sequentially sent from the multiple synchronization circuit 13 to the RAM 12. Therefore, writing starts from the position corresponding to the first write address of the main mark of TS 1, ends at address 20, and writes the 5th
The signal is written as shown in TS 1 of Figure (+11).

However, since the frame synchronization pattern of TS 2 starts with F and ends with F4 as described above, it is delayed by 5 frames compared to the standard frame synchronization pattern.

Therefore, the write address 5.6 is written from the multiple synchronization circuit 13.
...Sends the addresses corresponding to 4 to the RAM 12 in sequence. Therefore, as shown at TS 2 in FIG. 5(a), writing starts from the part marked with this mark and ends at F4.

Thereafter, input signals are written to the RAM in the same manner, so that when the writing is completed, the phases of the multi-frames match as shown in FIG. 5 (al).

After that, using the output of the counter 11, sequentially from F.

The read signals are sequentially written into the RAM 21 from Fl using the output of the counter 25 that has passed through the selector 22, for example.

Here, in FIG. 5 (bl is RAM1 in the frame aligner)
An example of write address-AddO for 2 is shown, the number on the left side is the TS number, and the number on the right side is the write address.

Now, as shown in Figure 5 (al), the RAM 23 written with the multi-frame phases aligned corresponds to the read address from the address control memory (not shown) in which the single line setting information is stored. are sequentially read out and output through the selector 27, but at this time,
If frame positions need to be replaced, the replacement is performed.

In addition, the selectors 22.24. When the inverter 26 is writing the input signal to one RAM, the inverter 26 writes the input signal to the other RAM.
This is a selector part for reading out signals written from the RAM, and thereby writing/reading is performed alternately in the two RAMs.

[Problem that the invention seeks to solve]

However, when a frame aligner is used, since the input signal is written/read here, there is a possibility that the input signal is delayed by one multiframe at most.

In addition, in recent years there has been a trend towards miniaturization of devices, and in response to this trend, there are two problems: the scale of this circuit needs to be made as small as possible.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 3 is a multiframe phase detection means for detecting the phase of each multiframe, and 5 is a multiframe phase detection means for detecting the phase of each multiframe when the multiframe is written into the storage means by using the output of the multiframe phase detection means. This is a write address generation means that generates a write address such that the phases of the two coincide with each other.

Further, at 4, a multi-frame structured signal is written corresponding to the output of the write address generating means.

This is a storage means from which the signal written corresponding to the input read address is read.

[Effect]

As explained above, the frame aligner with a large delay time uses the internal RAM 12 to write/read the input multi-frame signal. On the other hand, RAM 21. 23 is used for writing/reading, and the functions of one circuit are duplicated.

Therefore, in the present invention, a write address is generated from the write address generation means 5 using the output of the multi-frame phase detection means 3, and the above-mentioned input signal is written into the storage means 4 so that the phases of the multi-frames match. . Frame positions are swapped when reading signals written from this storage means, so if control to match the phases of multi-frames is performed at the time of writing, both can be done simultaneously without conflict.

This reduces the signal delay time.

The circuit scale is reduced.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the invention.

Here, the multiple synchronization circuit 31 is a component of the multi-frame phase detection means 3, RAM 41.43. Selector 42°44.45. The inverter 46 is a component of the storage means 4;
Conversion table 51. Counter 52 represents a component of write address generating means 5.

Below, the multiframe configuration is the same as the conventional example.

The operation will be explained as follows.

In the figure, the phases of the multi-frames are matched by converting the output of the counter 52 and the multi-frame phase information from the multiplex synchronization circuit 31 into write addresses via the address conversion table 51 using ROM. It has a frame aligner function.

That is, since the multiple synchronization circuit 31 sends an output indicating one of the 20 phase states that a multiframe can take to the conversion table 51, the conversion table 51 has an output of 1, for example, as shown in FIG. 5(b). Write addresses in the format shown in 20 ways per ITS for all TSs.

Then, a 5-bit signal for identifying 20 different phase states is output from the multiplex synchronization circuit 31.

This signal is used to select the corresponding first write address (the write address in the book part of FIG. 5(a)) from among all the write addresses written in the conversion table, and the output of the counter 52 is used to The write address for 20 frames is read out.

This makes the input signal l? Since the frames are sequentially written to the positions designated by the write addresses in the AM 41, the phases of the multi-frames match.

After that, the selector 42 and 44 are controlled by the selector control signal.
is driven, a read address including a frame position change from an address control memory (not shown) is added to the RAM 41, and an input signal written corresponding to this read address is read out.

That is, by integrating the frame position replacement part and the frame aligner, the delay time for the input signal is reduced and the scale of the nine circuits is reduced.

〔Effect of the invention〕

As described above in detail, the present invention has the effect of reducing the delay time for input signals and reducing the circuit scale.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a conventional example, Fig. 4 is a frame configuration diagram, and Fig. 5 is an explanation of frame aligner operation. Show the diagram. In the figure, 3 indicates multi-frame phase detection means, 4 indicates storage means, and 5 indicates write address generation means.

Claims (1)

[Claims] Each time slot constitutes a multiframe, and each multiframe is composed of signals of n frames (n is a positive integer), but when the phase is in an undefined state for each time slot, In a time switch circuit that switches frame positions within the n frames, a multi-frame phase detection means (3) detects the phase of each multi-frame, and an output of the multi-frame phase detection means is used to detect the phase of each multi-frame. Multi-frame storage method (4)
A write address generating means (5) generates a write address such that the phase of each multi-frame matches when writing to the input address, and a multi-frame configuration signal is written corresponding to the output of the write address generating means. 1. A time switch circuit comprising a storage means (4) from which the signal written in correspondence with the read address is read out.