JPH01191477A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To improve the current capacity of a field-effect transistor by one or two orders of magnitude at the same breakdown strength value and within the same dedicated area, by forming a gate in a ring shape, and increasing the circumferential length, i.e., e channel width, to a large extent. CONSTITUTION:An embedded semiconductor layer 2 and a p-type layer 3 are diffused in a semiconductor substrate 1. Thereafter, an n-type epitaxial layer is grown for a semiconductor region 4. The semiconductor region 4 is isolated from the semiconductor region 4 with an isolating and diffusing layer 5. Then, a connecting layer 6 is diffused. Thereafter, a p-type first semiconductor layer 7 is diffused in a double-ring shape. A gate 8 has a ring shape. The surface of each channel forming layer 7a of the double-ring shaped first semiconductor layer is commonly covered through a gate insulating film 8a. A second semiconductor layer 9 is formed in the inside of the layer 7. A drain terminal D, a source terminal S and a gate terminal G are led out of electrodes 11-13.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is suitable for incorporation into integrated circuit devices, and is suitable for use in field effect transistors or MOs with relatively large voltage and current capacities.
S) Regarding transistors.

[Conventional technology]

Field effect transistors or MOS transistors incorporated into the above-mentioned integrated circuits have been widely used for high-speed processing of digital signals, but recently, integrated circuits have been used to directly drive loads with large voltage and current capacity. Relatively large capacity field effect transistors, which can withstand a circuit voltage of 100 to 200 V and have a current capacity of several tens to several hundreds of mA, have come to be incorporated mainly in the final stage of the circuit. Field-effect transistors suitable for such applications require a structure different from conventional transistors for digital signal processing, but they can be fabricated into integrated circuits using the same process as small transistors, and can be made as small as 200 to 300 square meters. It is desirable to fit within the area. So-called DM
A field effect transistor called O3 satisfies this requirement and an example of its structure is shown in FIGS. 4 and 5. FIG. 4 is a sectional view of one field effect transistor of this type, and FIG. 5 is a top view thereof.

In FIG. 4, for example, p
A strong n-type layer for the buried semiconductor layer 22 and a strong p-type layer for the buried semiconductor layer 23 of the isolation diffusion layer are diffused in the upper surface of the shaped semiconductor substrate 21 at the location where the field effect transistor is to be fabricated. Then, an n-type evixital layer 24 having a relatively high resistance is grown to a predetermined thickness on the entire surface. A strong p
The n
The evixital layer 24 is formed on a p-type semiconductor substrate 2.
1. Embedded semiconductor I! The semiconductor region is junction-isolated from 23 and the isolation diffusion layer 25.

A field effect transistor is formed in this semiconductor region 24, but before that, a strong n-type connection layer 26 is formed from the surface in a circular shape to form a buried semiconductor Fi2 under the semiconductor region 24.
Diffuse deeply to reach 4. A drain terminal is later derived from this connection.

Next, in the circular area surrounded by this connection layer 26, a p-type first
The semiconductor N27 is annularly diffused, and a gate 28 is provided via a very thin gate insulating film 28 so as to cover the surfaces of the inner diameter portion and the inner hole portion as shown. Furthermore, by ion implantation using this gate as a mask, the n-type second semiconductor layer 29 is annularly diffused into the first semiconductor layer 27 .

Electrodes 31 to 33 are provided through windows in the insulating film 30 on the surface of the semiconductor substrate in which such a semiconductor layer is diffused. The electrode 31 is provided in an annular shape so as to be in conductive contact with the connection layer 26, and a drain terminal is led out from the electrode 31. The electrode 32 is provided in a ring shape so as to be in common conductive contact with the first semiconductor layer 27 and the second semiconductor layer 29, and a source terminal S is led out from the electrode 32. The electrode 33 is a circular electrode in conductive contact with the gate 28, from which a gate terminal G is led out. The field effect transistor constructed in this manner has a concentric structure with the gate electrode 33 at the center, as shown in FIG.

This field effect transistor is used, for example, by applying a positive voltage to the drain terminal and by grounding the source terminal S. The surface of the p-type first semiconductor Ji 27 below the gate 28 is a channel formation region, and therefore the field effect transistor in this example is of an n-channel type. When a positive driving voltage is applied to the gate terminal G, a channel is formed under the gate 28, and electrons are injected as carriers from the n-type second semiconductor layer 29 into the semiconductor region 24 through this channel.

In the figure, this injection current is indicated by ic. When the substrate is injected into the semiconductor region by this injection current ic, its conductivity increases.
2 to the first semiconductor layer 27. Semiconductor region 24. Drain electrode 31 via buried semiconductor layer 22 and connection 1i26
flows to Of course, this electron current ie is not sustainable by itself, but flows on the condition that the injection current ic exists.

[Problem to be solved by the invention]

The above-mentioned field effect transistor with the DMO3 structure is of course horizontal in terms of the injection current IC, and vertical in terms of the electron current ie, and operates as an image. Furthermore, since each semiconductor layer is generally annular and electric field concentration does not occur at sharp corners, it has the advantage of increasing the breakdown voltage of the entire structure. There is a problem that it becomes impossible to obtain a large current capacity. As can be easily understood, this breakdown voltage value is n
This is achieved by applying a reverse bias to the junction between the p-type semiconductor region 24 and the p-type first semiconductor layer 27. Therefore, in order to increase the withstand voltage value, a depletion layer is formed from this junction to the semiconductor region 24. It is necessary to lower the concentration of these impurities so that they can easily extend to the first semiconductor layer 27. However, when the impurity concentration is lowered, the resistance value increases, so the current
ie becomes difficult to flow and its contribution decreases.

In other words, even in this type of field effect transistor, there is a reciprocal relationship between increasing the withstand voltage and increasing the current.For example, under the condition that the diameter of the field effect transistor is suppressed to about 200 to 300 V, the withstand voltage value is 200 to 300 V or more. If you increase the current capacity to 1, you will only be able to obtain a current of less than a few mA.Of course, if you increase the diameter of the field effect transistor, you can increase the current capacity almost proportionally.
A large area is consumed in proportion to the square of the diameter to incorporate the field effect transistor into an integrated circuit or the like.

It is an object of the present invention to solve these problems and obtain a field effect transistor with high breakdown voltage and large current capacity without increasing the occupied area while retaining the advantages of DMO3.

[Means to solve the problem]

The present invention provides a field effect transistor having a DMOS structure, including a first semiconductor layer of one conductivity type annularly diffused from the surface of the semiconductor region of the other conductivity type, and a first semiconductor layer of the other conductivity type diffused from the surface of the first semiconductor layer into the first semiconductor layer. A second semiconductor layer of one conductivity type that is doubly diffused with the first semiconductor layer so as to leave annular surfaces on both the inner and outer sides of the first semiconductor layer in a concentric ring shape; By providing the remaining annular surface with an annular gate provided on the surface so as to be able to induce a channel, the above object has been successfully achieved.Of course, the field effect transistor according to the present invention also has the same advantages as the conventional one. Similarly, the first semiconductor layer and the second semiconductor layer commonly have one main terminal, for example, a source terminal, and the other main terminal, for example, a drain terminal.

[Effect]

In the conventional DMO5 structure field effect transistor described above, the gate is placed at the center of the semiconductor region, and the channel width, which is approximately determined by the perimeter of the gate, cannot be made very large. By forming the gate in an annular shape and greatly increasing its perimeter, or channel width, compared to conventional devices, we succeeded in increasing the current capacity of a field-effect transistor by one to two orders of magnitude within the same breakdown voltage and dedicated area. This is what I did.

In accordance with forming the gate in an annular shape, the present invention provides the first
The diameter of the semiconductor layer is larger than that of the conventional structure, and there are no sharp corners in the junction with the semiconductor region, which is advantageous in terms of high breakdown voltage. It is possible to increase the contribution rate of the current parallel to the current. Therefore, in the present invention, the current capacity of the field effect transistor is improved due to the increase in the injection current due to the increase in the channel width and the increase in this contribution. When forming a gate in an annular shape, there is an area margin at the center, so the drain connection layer 26, which was conventionally placed at the periphery of the semiconductor region 24 as shown in FIG. 4, is reversed. This central location within the semiconductor region is advantageous. This enables device design that effectively utilizes the area of the semiconductor region. Other advantageous embodiments of the invention can be found in the following section. [Example] The invention will now be described in detail with reference to FIGS. 1 to 3. FIG. FIG. 1 shows a cross section of an embodiment of a field effect transistor according to the present invention, and FIG. FIG.

In FIG. 1, the semiconductor substrate 1 in this embodiment is also of p-type, and one with a specific resistance of about several tens of ohms is usually used. After diffusing an n-type buried semiconductor layer 2 and a p-type buried semiconductor layer 3 to a sheet resistance of 10 to 20 Ω/hole, an n-type evixital layer is formed for the semiconductor region 4 by 20 to 3 Ω.
In this example, after the semiconductor region 4 is junction-separated from the semiconductor substrate by deeply diffusing the 6 strong p-type isolation diffusion layer 5, which is grown with an impurity concentration that gives a specific resistance of around 10 Ω (maximum) to a thickness of 0- A connection layer 6 for leading out the drain terminal as the other main terminal is deeply diffused from the surface of the center of the semiconductor region 4 in a strong n-type state so as to reach the buried semiconductor layer 2.

Now that the field effect transistor is ready to be fabricated, the p-type first semiconductor layer 7 is diffused into a double ring shape in this example. To obtain a pressure resistance value of 200 to 300■,
This first semiconductor layer is connected to a depth of about 10 tlfn by several hundred Ω.
It is best to diffuse it with a sheet resistance of about 1/2 inch. In addition, in such a high-voltage field effect transistor, for a channel formation portion below the gate 8 between the rings of the double-ring-shaped first semiconductor layer, a p-type continuous layer is formed as part of the first semiconductor N7. However, it is preferable to diffuse the channel forming layer 7a, which has a lower sheet resistance, to a depth approximately half that of the first semiconductor layer. The upper gate 8 is annular as mentioned above,
Each channel forming layer 7 of the first semiconductor layer having an inner and outer double ring shape
For example, polycrystalline silicon is grown to a thickness of about 0.5 - so as to commonly cover the surfaces of the gate insulating films 8 a with a gate insulating film 8 a that is about 0.1 - thick. The n-type second semiconductor layer 9 is diffused by ion implantation using this gate 8 as a mask as usual, and is diffused to a depth of 1 to 2-10Ω/2.
As shown in the figure, the semiconductor layer 7 is formed in a double ring shape inside the first semiconductor layer 7 with a sheet resistance as low as that of the semiconductor layer 7.

Now that the semiconductor layer and gate for the field effect transistor have been fabricated, the insulation layer 1f is deposited on top of the semiconductor layer and gate. A drain electrode 11 in this example for the other main terminal in conductive contact with the connection layer 6 and one main terminal in common conductive contact with the first semiconductor layer 7 and the second semiconductor layer 9 through the window of the JIO. A source electrode 12 for a terminal and a gate electrode 13 in conductive contact with the gate 8 are provided. These electrodes 11
As shown in the figure, a drain terminal as the other main terminal, a source terminal S and a gate terminal as the negative main terminals are derived from 13.

FIG. 2 (Al is a top view of the field effect transistor according to the present invention configured as described above, when the gate and semiconductor layer are formed in an annular shape.Contrary to the conventional case, the drain terminal is located in the semiconductor region. Further, it can be seen from the figure that the area of the circular semiconductor region surrounded by the partial region 5 is utilized very effectively in the field effect transistor according to the present invention. (bl is a top view of a field effect transistor in which a semiconductor region surrounded by an isolation diffusion layer 5 is made into a rectangular shape, and a gate and a semiconductor layer are formed in a rectangular ring shape. Since the electric field concentration at the corners is higher than in the case of the same figure (+1), it is somewhat disadvantageous in terms of withstand voltage, but instead, the concentration of the electric field at the four corners that were idle in the case of Since the area is more effectively utilized, it is possible to increase the current carrying capacity of the field effect transistor compared to the annular case.

In the embodiments shown in FIG. 1 and FIG.
The current capacity of a field effect transistor having a breakdown voltage value of ~300 V can be increased from the conventional 2-3 mA to about 25-40+sA.

In the above embodiments, the first semiconductor layer and the second semiconductor layer were formed in a double ring shape, but FIG. 3 shows an embodiment in which they are formed in a single ring shape. of course,
Although the number of rings is now 172, the current capacity is disadvantageous compared to the previous embodiment, but the area of the semiconductor region can be reduced accordingly. Except for this point, the rest is the same as the previous embodiment, so the explanation will be omitted.

The present invention is not limited to the embodiments listed above, and the present invention can be carried out in various forms.For example, the shape of the ring such as a gate is not limited to a circular ring or a rectangular ring, but can be made into an elliptical ring or a flat ring. A plurality of annular units can be built into the semiconductor region to increase the current capacity. At this time, the connection layer for leading out the disk storage device from the embedded semiconductor layer is not limited to the center of the semiconductor area, but may be distributed at the four corners of the semiconductor area, or may be formed into an elongated shape. It is possible to effectively utilize the area of the region. Furthermore, the conductivity type of each semiconductor layer in the embodiment can be reversed to make the field effect transistor a p-channel type.

〔Effect of the invention〕

As described above, in the present invention, a field effect transistor having a 0MO3 structure includes a first semiconductor layer of the other conductivity type which is annularly diffused from the surface of the semiconductor region of one conductivity type, and A second semiconductor layer of one conductivity type is doubly diffused with the first semiconductor layer so as to leave an annular surface on both the inner and outer sides of the first semiconductor layer in a concentric ring shape from the surface thereof, and A ring-shaped gate is provided on the surface of the remaining ring-shaped surface so as to be able to induce a channel, and one main terminal is commonly connected from the first semiconductor layer and the second semiconductor layer. Since the other main terminals are each led out from the semiconductor region, the gate width is significantly increased compared to the conventional one, and the high withstand voltage electric field created within the semiconductor region of the same size or area as the conventional one. According to the present invention, the current capacity of the effect transistor can be increased by 1 to 1 compared to the conventional one.
It can be increased by two orders of magnitude. This is because not only the current injected into the semiconductor region increases as the gate width increases, but also the contribution ratio of the parallel current based on the injection current can be improved compared to the conventional method as described above.

In implementing the present invention, only by changing the diffusion pattern of each semiconductor layer and the shape of the gate from the conventional one, a field effect transistor with a large current capacity can be incorporated into an integrated circuit device using the same manufacturing process as the conventional one. The invention is an integrated circuit that directly drives relatively high voltage and large current loads;
For example, it can be applied to an integrated circuit device for driving a plasma display panel, and the above effects can be most advantageously exhibited.

[Brief explanation of the drawing]

1 to 3 relate to the present invention, in which FIG. 1 is a cross-sectional view of one embodiment of a field effect transistor according to the present invention, and FIG.
3 is a top view thereof, and FIG. 3 is a sectional view of a field effect transistor showing a different embodiment of the present invention. 4 and subsequent figures relate to the prior art. FIG. 4 is a cross-sectional view of a conventional field effect transistor with an MO3 structure, and FIG. 5 is a top view thereof. Semiconductor layer, 3:
Embedded semiconductor layer for isolation diffusion layer, 4: semiconductor region or evixital layer, 5 isolation diffusion layer, 6: connection layer, 7: first semiconductor layer, 7a: channel forming layer, 8X game), 8a
: Gate single-color edge film, 9: Second semiconductor layer, 10: Insulating film, 11 to 13: Electrode, 21: Semiconductor substrate, 22.23
: Buried semiconductor layer, 24: Semiconductor region or evixital layer, 25: Isolation diffusion layer, 26: Connection layer, 27: First
semiconductor layer, 28: gate, 28a: gate insulating film, 2
9: second semiconductor layer, 30: insulating film, 31 to 33: electrode, D: drain terminal as the other main terminal, G: gate terminal, ic: injection current, te: parallel current to injection current, Sni One of the main terminals is the source terminal. Figure 1 (a) (b) Figure 2

Claims (1)

[Scope of Claims] 1) A first semiconductor layer of the other conductivity type diffused into a semiconductor region of one conductivity type in an annular shape from the surface thereof, and a first semiconductor layer of the other conductivity type diffused in a concentric ring shape from the surface into the first semiconductor layer. and a second semiconductor layer of one conductivity type doubly diffused with the first semiconductor layer so as to leave ring-shaped surfaces on both the inner and outer sides, and a second semiconductor layer of one conductivity type left on either the inner or outer side of the first semiconductor layer. an annular gate provided on the annular surface to be able to guide a channel into the annular surface;
A field effect transistor in which one main terminal is commonly led out from a first semiconductor layer and a second semiconductor layer, and the other main terminal is led out from a semiconductor region. 2) In the field effect transistor according to claim 1, the field effect transistor is for incorporation into an integrated circuit device, and the semiconductor region is a partial region junction-separated from a semiconductor substrate of the other conductivity type, A field effect transistor characterized in that the other main terminal is led out from the surface of the semiconductor region as this partial region. 3) In the field effect transistor according to claim 1, a buried semiconductor layer of one conductivity type buried under the first semiconductor layer for leading out the other main terminal from the semiconductor region. and a connection layer diffused so as to communicate with the buried semiconductor layer from the surface of the semiconductor region, and the other main terminal is led out from the connection layer. 4) The field effect transistor according to claim 1, wherein the other main terminal is led out from inside the annular first semiconductor layer. 5) In the field effect transistor according to claim 1, a double ring consisting of a first semiconductor layer and a second semiconductor layer is provided on an inner and outer side, and an annular ring is provided for both double rings. A field effect transistor characterized in that a gate is provided in common.