JPH01196176A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain high reliability, high breakdown strength and high driving capacity as compared with a conventional LDD structure by specifying the order of impurity concentration values among a first impurity region to a third impurity region and by specifying a diffusion region. CONSTITUTION:For example, a gate electrode 3 is formed on a P-type silicon substrate 1 via a gate oxide film 2. Phosphorus is implanted by making use of the gate electrode as a mask; a first diffusion region 4 is formed. Side-wall bodies 5 of SiO2 are formed on side walls of the gate electrode 3; arsenic is diffused doubly in a self-aligned manner by making use of the side-wall bodies 5 as a mask; a second diffusion region and a third diffusion region 6, 7 are formed. The concentration value of the first diffusion region is set to be lower than that of the second diffusion region; the concentration value of the second diffusion region is set to be lower than that of the third diffusion region; the diffusion length in the transverse direction of the first diffusion region is set in such a way that the diffusion length in the transverse direction of the second diffusion region does not exceed that of the first diffusion region; the diffusion length in the transverse direction of the second diffusion region is set in such a way that the diffusion length in the transverse direction of the third diffusion region does not exceed that of the second diffusion region; in addition, the diffusion length in the depth direction of the second diffusion region is set in such a way that it does not exceed the diffusion length in the depth direction of the third diffusion region.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to lightly doped drains (lightly doped drains).
Try Doped Drain (hereinafter referred to as LDD)
The present invention relates to a MIS type semiconductor device having a structure.

<Prior Art> Recently, as the integration of MIS semiconductor devices has progressed, the breakdown voltage of the transistors has decreased and reliability has decreased due to hot carriers.In order to solve these problems, the drain region 2 of the low concentration and high concentration diffusion regions
A MIS type semiconductor device with a layered LDD structure has been developed and put into practical use.<Problems to be solved by the invention> The low concentration diffusion region of the above LDD structure suppresses the generation of hot carriers by relaxing the drain electric field. However, on the other hand, there is a problem in that the current driving ability decreases due to an increase in parasitic resistance due to the low concentration diffusion region. In addition, as elements become smaller and the substrate concentration increases, there is a problem in that the withstand voltage of the source and drain junctions deteriorates.

The present invention is an MIS type semiconductor device for solving the above problems.

<Means for Solving the Problems> The present invention provides a gate electrode provided on a semiconductor substrate of a first conductivity type via a gate insulating film, and a second conductivity type different from the semiconductor substrate using the gate electrode as a mask. In an MIS type semiconductor device having source and drain regions formed by implanting impurity ions of a conductivity type, the first diffusion region is formed by implanting impurity ions of a second conductivity type using the gate electrode as a mask. and then providing a side wall body made of an insulating material on the side wall of the gate electrode,
By doubly diffusing impurities of the second conductivity type with different diffusion coefficients in a self-aligned manner using the side wall body as a mask,
Second. A third diffusion region is formed, the first diffusion region is set to have a lower concentration than the second diffusion region, the second diffusion region is set to a lower concentration than the third diffusion region, and the lateral diffusion length of the first diffusion region is set to be lower than that of the second diffusion region. is set so that the lateral diffusion length of the second diffusion region does not exceed and the lateral diffusion length of the third diffusion region does not exceed the depth of the second diffusion region. It is characterized in that the direction diffusion length is set to exceed the depth direction diffusion length of the third diffusion region.

<Action 2 of the Invention According to the present invention, similarly to the above-mentioned LDD structure, generation of hot carriers can be suppressed, current driving power can be prevented from decreasing due to increase in parasitic resistance, and breakdown voltage deterioration of the source-drain junction can be prevented. High-performance, high-reliability, and high-voltage MIS that prevents
type semiconductor device can be obtained.

<Example> An example in which the present invention is applied to an n-channel MO3IC will be described below, with process cross-sectional views shown in FIGS. 1 to 3.

First, as shown in FIG.
After depositing a gate oxide film 2 with a thickness of 00λ and an n-type polycrystalline silicon film with a thickness of 13sooX, a gate electrode 3 is formed by photoetching. After that, using the gate electrode 3 as a mask, phosphorus was accelerated at a voltage of 40 keV and at a dose of 3X.
It is implanted under conditions of 10 am and activated to form the first diffusion region 4 in a self-aligned manner.

In this embodiment, an n-type polycrystalline silicon film is used as the material for the gate electrode 3, but a polycide film, a p-type polycrystalline silicon film, or a p-type polycrystalline silicon film may also be used.

Next, a 5i02 film having a thickness of 2500X is deposited on the entire surface, and the entire surface is etched by a reactive ion etching method to form a sidewall body 5 made of 5io2 adjacent to the gate electrode 3, as shown in FIG.

Next, using the gate electrode 3 and side wall body 5 as a mask, g
As shown in Figure 3, phosphorus was doubly implanted at an accelerating voltage of 60 keV and a dose of lXl0 am, and arsenic, which has a smaller diffusion coefficient than phosphorus, was doubly implanted at an accelerating voltage of 50 keV and a dose of 5 Oa, and diffused at 900°C for 40 minutes. and double diffusion to form a second diffusion region 6 and a third diffusion region 7. By forming through the above steps, the first to third diffusion regions 4. 6. 7, the impurity concentration of the first diffusion region 4 can be set lower than the concentration of the second diffusion region 6, and the concentration of the second diffusion region 6 can be set lower than the concentration of the third diffusion region 7, and Set so that the lateral diffusion length of the second diffusion region 6 does not exceed the lateral diffusion length of the second diffusion region 6, and the lateral diffusion length of the third diffusion region 7 does not exceed the lateral diffusion length of the second diffusion region 6. Furthermore, the depth of the second diffusion region 6 can be set to exceed the depth of the third diffusion region 7.

In this embodiment, simultaneous implantation and simultaneous diffusion are performed to form the second diffusion region and the third diffusion region, but the implantation and diffusion may be performed separately.

In this embodiment, an example in which n-channel MO8ICvC is applied has been described, but it can also be applied to CMO8IC and the like.

<Effects of the Invention> As detailed above, according to the present invention, it is possible to provide a MIS type semiconductor device that has higher reliability, higher breakdown voltage, and higher driving ability than the conventional LDD structure.

[Brief explanation of the drawing]

1 to 3 are cross-sectional views of manufacturing steps in an embodiment of the present invention. 1...P-type silicon substrate 2...Gate oxide film 3...Gate electrode 4...N-type diffusion region (first diffusion region) 5...Side wall body 6...N-type diffusion region (second diffusion region) Area) 7...N-type diffusion area (third diffusion area) Agent Patent attorney Takeshi Sugiyama (and one other person) Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. In a semiconductor device in which source and drain regions are formed by implanting impurities of a conductivity type different from that of the semiconductor substrate into a semiconductor substrate using a gate electrode as a mask, the source and drain regions mask the gate electrode. a first impurity region implanted into the same region, a second impurity region implanted using a gate electrode with an insulator added to the sidewall as a mask, and a third impurity region implanted with an impurity having a diffusion coefficient different from that of the second impurity region into almost the same region. In the impurity regions, the impurity concentration is set to be high in the order of the first, second, and third impurity regions, and the lateral diffusion length of the first impurity region exceeds the lateral diffusion length of the second impurity region. First, a MIS type semiconductor device characterized in that the depthwise diffusion length of the second impurity region is diffused to exceed the depthwise diffusion length of the third impurity region.