JPH0119648B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gain control device configured using a differential amplifier, and in particular provides a gain control device that can freely control the magnitude of gain while keeping the gain control ratio constant. It is.

FIG. 1 shows a circuit diagram of an embodiment of the present invention. To explain this, 1 and 2 are transistors that constitute the first differential amplifier 31;
is an input terminal that applies a differential voltage to the bases of transistors 1 and 2, 5 and 6 are load resistances of the first differential amplifier 31, 7 is a collector bias power supply,
8 is an output terminal; 9 and 10 are input terminals for applying a differential voltage to the bases of transistors 11 and 12 forming the second differential amplifier 32; and 13 and 14 are transistors forming the third differential amplifier 33. In order to switch 15 and 16, an input terminal applies a differential voltage to the bases of transistors 15 and 16, 17 is a transistor that constitutes a current source, 18 is an emitter resistance of transistor 17, and 19 is a base of transistor 17. A bias resistor, 20 a base bias power supply, 21 a coupling capacitor, and 22 an input terminal to which an input signal is applied.

Next, the operation of this embodiment will be explained.

Since the input signal applied to the input terminal 22 is applied to the base of the transistor 17 via the coupling capacitor 21, the collector current of the transistor 17 contains the signal, and this current flows to the emitters of the transistors 15 and 16. By the way, normally, the voltage applied to the input terminal 13 is
Since the voltage is higher than that of transistor 4, transistor 15 is conductive and transistor 16 is in a cut-off state. At this time, the collector current of transistor 17 becomes equal to the collector current of transistor 15, and this current flows to the emitters of transistors 1 and 2. A DC voltage is applied to input terminals 3 and 4 of the bases of transistors 1 and 2, and by changing the difference between these two DC voltages, the ratio of collector currents of transistors 1 and 2 is controlled. In accordance with this base voltage difference, current flowing through the collectors of transistors 1 and 2 flows through load resistors 5 and 6, and is taken out as an output signal at output terminal 8.

In the third differential amplifier 33, the input terminal 14
When the voltage applied to input terminal 13 is higher than that of input terminal 13, transistor 16 becomes conductive, transistor 15 becomes conductive, and the collector current of transistor 17 becomes equal to the collector current of transistor 16, and this current flows through transistors 11 and 12. Flows into Emitsuta. A DC voltage is applied to input terminals 9 and 10 coupled to the bases of transistors 11 and 12, and by changing the difference between these two DC voltages, the ratio of collector currents of transistors 11 and 12 is controlled. The collector current of transistor 11, which flows in accordance with this voltage difference, flows to the emitters of transistors 1 and 2. As mentioned above, the current flowing to the collectors of transistors 1 and 2 can be changed by changing the difference in DC voltage between input terminals 3 and 4, which are connected to the bases of transistors 1 and 2. flows through load resistors 5 and 6, and is taken out as an output signal at output terminal 8.

In such a circuit configuration, load resistors 5 and 6
The resistance values of the emitter resistor 18 of the transistor 17 are R ₅ and R ₆ , respectively, and the resistance value of the emitter resistor 18 of the transistor 17 is R ₁₈ , and h _FE of each transistor is sufficiently large.
Assume that the base current is negligible.

FIG. 2 shows the gain control characteristics when the transistor 15 is in a conductive state and the transistor 16 is in a cut-off state in the circuit configuration shown in FIG. This is the voltage difference between the voltages, and this is defined as V _S. The vertical axis represents gain. The side (right side) indicates that the voltage of input terminal 3 is higher than input terminal 4, and the side (left side)
indicates that the voltage at input terminal 3 is lower than that at input terminal 4. The maximum value G ₁ of the gain is when all the collector current of transistor 17 flows to transistor 15 and then all flows to the collector of transistor 1 (when input terminal 3 is higher than input terminal 4), and G ₁ = (R ₅ + R ₆ )/R ₁₈ times.
When V _S =0, the collector current of transistor 17 is equally divided into transistors 1 and 2, so the gain value G ₂ is G ₂ =(R ₅ /2+R ₆ )/R ₁₈ times.

The minimum gain value _G3 is when the voltage at input terminal 3 is lower than the voltage at input terminal 4, and transistor 1
7 collector currents all flow to transistor 2, so G ₃ = R ₆ /R ₁₈ times.

FIG. 3 is a gain control characteristic diagram when the transistor 16 is on and the transistor 15 is off. In FIG. 3, the horizontal and vertical axes represent V _S and gain, respectively, as in FIG. 2, and graph A is the same characteristic diagram as in FIG. The characteristic diagram is exactly the same as when the transistor 11 is turned off, the transistor 11 is conductive, and the transistor 12 is cut off. The collector current of transistor 16 is shunted to transistors 11 and 12 by the voltage applied to input terminals 9 and 10. The ratio of the collector current of transistor 11 and the collector current of transistor 12 is k ₁ /(1−k ₁ )
Then, k ₁ of the collector current of transistor 17
Since the multiplied amount flows to transistor 11 and is further supplied to the emitters of transistors 1 and 2, the gain at this time becomes as shown in graph B of FIG. That is, the gains G ₁ , G ₂ , G ₃ are each
k ₁ G ₁ , k ₁ G ₂ , k ₁ G ₃ . Graph C represents the case where the current ratio is k ₂ /(1-k ₂ ), and the gains are k ₂ G ₁ , k ₂ G ₂ , k ₂ G ₃ for graph C, respectively.
It is becoming.

As described above, according to the present invention, the first differential amplifier performs gain control, the second differential amplifier selects the gain control characteristic curve, and the third differential amplifier performs gain control.
By using the differential amplifier, a gain control device having a function of determining whether or not to select a gain control characteristic curve can be obtained. On this chosen curve, no matter what V _S is, the gain is always
On a curve (for example, graphs B and C), graph A
It has a constant value (for example, k ₁ or k ₂ ) for the above gain.

It goes without saying that the gain control characteristics can be easily changed by inserting a resistor into each emitter of the transistors constituting the second and third differential amplifiers. Furthermore, the gain can also be controlled by varying the DC voltages applied to the input terminals 3 and 4 and the input terminals 9 and 10.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
3 and 3 are gain control characteristic diagrams in the embodiment of FIG. 1. 1, 2, 11, 12, 15, 16, 17...transistor, 3, 4, 9, 10, 13, 14, 2
2...Input terminal, 5, 6...Load resistance, 7...Collector bias power supply, 8...Output terminal, 18...
Emitter resistance, 20...Base bias power supply, 3
1...first differential amplifier, 32...second differential amplifier, 33...third differential amplifier.

Claims (1)

[Claims] 1. One collector of a second differential amplifier is connected to a common emitter terminal of a first differential amplifier having an output terminal at the collector, and the other collector of the second differential amplifier is connected to a power supply terminal, One collector of a third differential amplifier is connected to the common emitter terminal of the first differential amplifier, and the other collector of the third differential amplifier is connected to the common emitter terminal of the second differential amplifier. and a first input signal is supplied to a common emitter terminal of the third differential amplifier, a second input signal is supplied to a base of the third differential amplifier, and the second input signal is supplied to the base of the third differential amplifier. Gain control is performed by the first differential amplifier, and the second differential amplifier performs gain control.
The third differential amplifier is configured to select a gain control characteristic curve, and the third differential amplifier determines whether or not to select a gain control characteristic curve. gain control device.