JPH01196855A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01196855A JPH01196855A JP63021240A JP2124088A JPH01196855A JP H01196855 A JPH01196855 A JP H01196855A JP 63021240 A JP63021240 A JP 63021240A JP 2124088 A JP2124088 A JP 2124088A JP H01196855 A JPH01196855 A JP H01196855A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum pad
- chip
- pressure applied
- time
- cross
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、バンプ付半導体チップに対して実装時に加わ
る圧力の限界値の向上を図った半導体装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device in which the limit value of pressure applied to a bumped semiconductor chip during mounting is improved.
（従来の技術）
近年、電子機器の小型化が要求される中にあって、半導
体集積回路の実装技術としてバンプ技術が注目されてい
る。従来のバンプ構造とその製造方法の一例を第２図に
示す。同図は従来のバンプ構造の断面図であり、シリコ
ン基板１の上に厚さ１〜２μｍ程度のいわゆるフィール
ド酸化Ｂ２が形成され、そのとにアルミパッド３が形成
されている。近年、ドライエツチング技術が進歩し、ア
ルミニウム膜のエツチングにも通常異方性の強いドライ
エツチングが用いられる。そのため、通常アルミパッド
３の端の断面形状は、フィールド酸化膜２に対して垂直
に近い切り立った形状になっている。アルミパッド３の
上からシリコン窒化膜などの表面保護膜４を形成したの
ち、アルミパッド３上の表面保護膜４を、図に示すよう
に選択的に除去する。さらに、チタンまたはパラジウム
などをアルミパッド３上に選択的に形成し、バリアメタ
ル５を形成する。そののちに、金などをメツキなどの方
法を用いてｌＯ〜２０ｐｍ程度アルミパッド：３上に選
択的にバンプ６を成長させることにより、第２図に示す
ようなバンプ構造が得られる。(Prior Art) In recent years, with the demand for miniaturization of electronic devices, bump technology has been attracting attention as a mounting technology for semiconductor integrated circuits. An example of a conventional bump structure and its manufacturing method is shown in FIG. This figure is a cross-sectional view of a conventional bump structure, in which a so-called field oxide B2 having a thickness of about 1 to 2 μm is formed on a silicon substrate 1, and an aluminum pad 3 is formed therebetween. In recent years, dry etching technology has advanced, and dry etching with strong anisotropy is usually used for etching aluminum films. Therefore, the cross-sectional shape of the end of the aluminum pad 3 usually has a steep shape nearly perpendicular to the field oxide film 2. After forming a surface protection film 4 such as a silicon nitride film on the aluminum pad 3, the surface protection film 4 on the aluminum pad 3 is selectively removed as shown in the figure. Further, titanium, palladium, or the like is selectively formed on the aluminum pad 3 to form the barrier metal 5. Thereafter, bumps 6 are selectively grown on the aluminum pad 3 to a thickness of about 10 to 20 pm using a method such as gold plating, thereby obtaining a bump structure as shown in FIG. 2.
（発明が解決しようとする課題）
上記、従来のバンプ構造では、バンプ付チップ実装工程
の一つであるＩ Ｌ Ｂ （Ｉｎｎｅｒ Ｌｅａｄ Ｂ
ｏｎｄ−ｉｎｇ）工程時に、アルミパッド部に３００〜
５００℃の温度でｌ（ｔ／ａ＃）以上の圧力が加わった
場合、アルミパッドが変形を起こし、その応力がアルミ
パッド端部に集中し、それを表面保護膜が押えきれずに
アルミパッド端部で表面保護膜にクラックが生じ、デバ
イスの信頼性上問題となるため、ＩＬＢ工程時にバンプ
とリード材料を接着するために加える圧力が制限される
欠点があった。(Problems to be Solved by the Invention) In the above-mentioned conventional bump structure, ILB (Inner Lead B), which is one of the steps for mounting a chip with bumps,
300~ to the aluminum pad part during the ond-ing) process.
If a pressure of 1 (t/a#) or more is applied at a temperature of 500°C, the aluminum pad will deform, and the stress will concentrate on the edge of the aluminum pad, and the surface protective film will not be able to suppress it, causing the aluminum pad to deform. Cracks occur in the surface protection film at the edges, which poses a problem in terms of device reliability.Therefore, there is a drawback that the pressure applied to bond the bump and lead material during the ILB process is limited.
本発明の目的は、従来の欠点を解消し、バンプ付半導体
チップの実装工程の一つであるＩＬＢ工程で半導体チッ
プに加える圧力の加圧限界を向上させることができる優
れた半導体装置を提供することである。An object of the present invention is to provide an excellent semiconductor device that can eliminate the conventional drawbacks and improve the pressure limit of the pressure applied to a semiconductor chip in the ILB process, which is one of the mounting processes for semiconductor chips with bumps. That's true.
（課題を解決するための手段）
本発明の半導体装置は、半導体チップの実装手段の一つ
であるバンプの構造において、アルミパッドの端の断面
形状がテーパー角度５０″以下のスロープ状にするもの
である。(Means for Solving the Problems) The semiconductor device of the present invention has a bump structure, which is one of the means for mounting semiconductor chips, in which the cross-sectional shape of the end of the aluminum pad is sloped with a taper angle of 50'' or less. It is.
（作 用）
上記構成により、従来のバンプ構造では、ＩＬＢ工程時
に加える圧力の上限に制限を受けていたものが、より高
い圧力がＩＬＢ工程を実施することが容易となり、信頼
性の高い安定した実装を行うことが可能となる。(Function) With the above configuration, the conventional bump structure was limited by the upper limit of the pressure applied during the ILB process, but it is now possible to easily perform the ILB process with a higher pressure, resulting in a highly reliable and stable bump structure. It becomes possible to carry out implementation.
（実施例） 本発明の一実施例を第１図に基づいて説明する。(Example) An embodiment of the present invention will be described based on FIG.
第１図は本発明のバンプ構造の断面図である。バンプを
形成するための製造工程および材料は、第２図に示した
従来例と基本的には相違なく、第１図の各部に付した符
号は、第２図の従来例に示したものと同一符号を付し、
その説明を省略する。FIG. 1 is a sectional view of the bump structure of the present invention. The manufacturing process and materials for forming the bumps are basically the same as those in the conventional example shown in Fig. 2, and the symbols given to each part in Fig. 1 are the same as those in the conventional example shown in Fig. 2. With the same symbol,
The explanation will be omitted.
第１図において、アルミパッド３を形成する際のエツチ
ングにウェットエツチングを採用し、等方的なエツチン
グを行うことにより、第２図に示した従来例ではアルミ
パッド３の端の断面形状がフィールド酸化膜２に対して
垂直に近い切り立った形状であるのに対し、第１図に示
した本発明によるバンプ構造では、アルミパッド３の端
の断面形状がテーパー角度５０°以下のスロープ状にな
っている。こういう構造にすることにより、ＩＬＢ工程
時に加わる圧力のために生じるアルミパッド３の端部の
応力集中を緩和することができ、ＩＬＢ工程時の加圧限
界を向上させることができる。In Fig. 1, wet etching is adopted for etching when forming the aluminum pad 3, and by performing isotropic etching, the cross-sectional shape of the end of the aluminum pad 3 is changed to a field shape in the conventional example shown in Fig. 2. In contrast, in the bump structure according to the present invention shown in FIG. 1, the cross-sectional shape of the end of the aluminum pad 3 has a slope shape with a taper angle of 50 degrees or less, whereas it has a steep shape almost perpendicular to the oxide film 2. ing. With this structure, it is possible to alleviate the stress concentration at the end of the aluminum pad 3 caused by the pressure applied during the ILB process, and it is possible to improve the pressure limit during the ILB process.
第２図に示した従来例の構造では、ＩＬＢ工程時にアル
ミパッド３に加わる圧力を１（ｔ／ａＪ）以上にすると
、アルミパッド３の端部付近で表面保護膜４にクラック
が生じるなど実装上問題があったが、第１図に示すよう
に、アルミパッド３の端部の形状をテーパー角度５０°
以下のスロープ状にすることにより、ＩＬＢ工程時にア
ルミパッド３に加わる圧力を１（ｔ／ａｊ）以上にして
も問題は生じない。In the conventional structure shown in FIG. 2, if the pressure applied to the aluminum pad 3 during the ILB process is greater than 1 (t/aJ), cracks may occur in the surface protection film 4 near the ends of the aluminum pad 3, etc. However, as shown in Fig. 1, the shape of the end of the aluminum pad 3 was changed to a taper angle of 50°.
By forming the following slope shape, no problem occurs even if the pressure applied to the aluminum pad 3 during the ILB process is increased to 1 (t/aj) or more.
（発明の効果）
本発明によれば、バンプ付半導体チップの実装工程の−
っであるＩＬＢ工程で半導体チップに加える圧力の加圧
限界を向上させることができ、信頼性の高い安定した実
装が可能となり、その実用上の効果は大である。(Effects of the Invention) According to the present invention, -
It is possible to improve the pressure limit of the pressure applied to the semiconductor chip in the ILB process, which enables highly reliable and stable mounting, and has great practical effects.
第１図は本発明の一実施例における半導体装置の断面図
、第２図は従来の半導体装置の断面図である。
１・・・シリコン基板、 ２・・・フィールド酸化膜、
３・・・アルミパッド、 ４・・・表面保護膜、 ５
・・・バリアメタル、 ６・・・バンプ。
特許出願人 松下電子工業株式会社
第１図
１−シリコン差」及
２−．７４−九、）！ 酸イ乙へ１１
３−７ル己バ・ｌド
４−へｊ抗水６ｖ艮
５−パー７メタル
６、−バンク。
第２図FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 1... Silicon substrate, 2... Field oxide film,
3... Aluminum pad, 4... Surface protective film, 5
... Barrier metal, 6... Bump. Patent applicant Matsushita Electronics Co., Ltd. Figure 1 1-Silicon Difference' and 2-. 74-9, )! Acid E Oto 11 3-7 Rui Bas L Do 4-J Anti-Water 6 V Ryo 5- Par 7 Metal 6, - Bank. Figure 2
Claims (1)
おいて、アルミパッドの端の断面形状がテーパー角度５
０゜以下のスロープ状であることを特徴とする半導体装
置。In the bump structure, which is one of the means for mounting semiconductor chips, the cross-sectional shape of the end of the aluminum pad has a taper angle of 5.
A semiconductor device characterized by having a slope shape of 0° or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63021240A JP2789467B2 (en) | 1988-02-02 | 1988-02-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63021240A JP2789467B2 (en) | 1988-02-02 | 1988-02-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01196855A true JPH01196855A (en) | 1989-08-08 |
| JP2789467B2 JP2789467B2 (en) | 1998-08-20 |
Family
ID=12049529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63021240A Expired - Lifetime JP2789467B2 (en) | 1988-02-02 | 1988-02-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2789467B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0277133A (en) * | 1988-09-13 | 1990-03-16 | Hitachi Ltd | Semiconductor device |
| JP2012243984A (en) * | 2011-05-20 | 2012-12-10 | Fujikura Ltd | Semiconductor device and manufacturing method of the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57139943A (en) * | 1981-02-23 | 1982-08-30 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
| JPS60117648A (en) * | 1983-11-30 | 1985-06-25 | Hitachi Ltd | Pattern forming method |
-
1988
- 1988-02-02 JP JP63021240A patent/JP2789467B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57139943A (en) * | 1981-02-23 | 1982-08-30 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
| JPS60117648A (en) * | 1983-11-30 | 1985-06-25 | Hitachi Ltd | Pattern forming method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0277133A (en) * | 1988-09-13 | 1990-03-16 | Hitachi Ltd | Semiconductor device |
| JP2012243984A (en) * | 2011-05-20 | 2012-12-10 | Fujikura Ltd | Semiconductor device and manufacturing method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2789467B2 (en) | 1998-08-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100367451C (en) | Semiconductor device and method for manufacturing the same | |
| CN100334711C (en) | Backside metallization on sides of microelectronic dice for effective thermal contact with heat dissipation devices | |
| TWI242807B (en) | Method for manufacturing semiconductor device | |
| CN100355036C (en) | Manufacturing method of semiconductor device | |
| JP3409759B2 (en) | Manufacturing method of semiconductor device | |
| JP3459234B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN1825590B (en) | Semiconductor device and manufacturing method thereof | |
| JP2753696B2 (en) | Automatic bonding structure of semiconductor package tape | |
| US7405139B2 (en) | Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch | |
| JPH01196855A (en) | Semiconductor device | |
| JPH01140652A (en) | Three-dimensional semiconductor device | |
| JPH03293740A (en) | How to connect semiconductor devices | |
| JP3179970B2 (en) | Resin-sealed semiconductor device and method of manufacturing the same | |
| JPH01196148A (en) | Semiconductor device | |
| US20070042568A1 (en) | Semiconductor device with a thinned semiconductor chip and method for producing the thinned semiconductor chip | |
| US6320269B1 (en) | Method for preparing a semiconductor wafer to receive a protective tape | |
| JP3019065B2 (en) | Semiconductor device connection method | |
| JPH01164041A (en) | Ic element having bump structure and its manufacture | |
| JP2000195887A (en) | Electronic components | |
| JPH01196147A (en) | Semiconductor device | |
| JPS5848445A (en) | Manufacture of film carrier | |
| JP4522213B2 (en) | Manufacturing method of semiconductor device | |
| JPH01196146A (en) | Semiconductor device | |
| JP3314662B2 (en) | Method of forming bump | |
| US20020106903A1 (en) | Manufacturing method of semiconductor device |