JPH01199473A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain an excellent-quality transistor with a high-precision gate electrode built in a simplified way incorporating self-alignment by a method wherein a dummy gate electrode is built of a first insulating layer, a second insulating layer is formed on its surface, then the dummy gate electrode is removed, and an opening is provided for the formation of a gate metal layer. CONSTITUTION:At a specified location on a semiconductor substrate 1 wherein an active layer 2 has been formed, a dummy gate electrode 3 is built of a first insulating layer 3 and, on its surface, a second insulating layer 4 is formed, which is selectively implanted with a specified impurity for the formation of a high-concentration impurity layer 5. Next, on the high-concentration impurity layer 5, an ohmic electrode layer 6 is formed, and then a photoresist layer 7 is formed, which is subjected to flattening. Etching-back is accomplished for the removal of the dummy gate electrode 3. An opening is provided, wherein a gate metal layer 8a is formed. A process follows wherein the lift-off method is applied for the removal of unnecessary parts from the gate metal layer 8a and for the removal of the photoresist layer 7 for the formation of a gate electrode 8. The first insulating layer 3 may be a silicon oxide layer, and the second insulating layer 4 may be a silicon nitride layer.

Description

[Detailed description of the invention] [Industrial application field] The present invention is utilized in the field of semiconductor devices.

The present invention relates to a method of manufacturing a field effect transistor, and particularly to a method of manufacturing a gate electrode of a field effect transistor that requires microfabrication.

〔overview〕

The present invention provides a method for manufacturing a field effect transistor, in which a gate electrode is formed by first forming a dummy electrode using a first insulating layer, forming a second insulating layer thereon, and then forming a dummy electrode using a first insulating layer. The layer position or the top eave position of the overlay gate can be determined, and the gate electrode is
By reversing the pattern of the first insulating layer and forming it by lift-off in a self-aligned manner, the process is simplified and the electrode position accuracy is improved.

[Conventional technology]

Conventionally, a method for manufacturing this type of field effect transistor has used a method in which a gate portion is opened in an insulating layer and a gate metal is deposited. In this manufacturing method, (1) the gate portion is determined between the two n+ type layers of the contact portion by alignment, (2) gate metal is deposited after opening, and the position of the overlay is further determined by alignment.

[Problem that the invention seeks to solve]

In the conventional field effect transistor manufacturing method described above,
It was very difficult to align the above-mentioned (1) and (2) for resist exposure, and there was a drawback of poor accuracy. In addition, in order to pattern with resist, the n-type layer distance or the size of the overlay must be widened, which has the disadvantage of reducing the source resistance or increasing the gate-drain capacitance. .

An object of the present invention is to eliminate the above-mentioned drawbacks, thereby making it possible to easily and precisely form a gate electrode in a self-aligned manner without requiring difficult alignment, and to obtain a transistor with excellent characteristics. An object of the present invention is to provide a method for manufacturing an effect transistor.

[Means for solving problems]

The present invention provides a method for manufacturing a field effect transistor including a step of forming a gate electrode, in which the step of forming the gate electrode includes forming a first insulating layer at a predetermined position on a semiconductor substrate on which an active layer is formed. forming a dummy target electrode, forming a second insulating layer on the surface of the second insulating layer, and selectively implanting a predetermined impurity into the second insulating layer to form a high concentration impurity layer; and forming an ohmic electrode on the high concentration impurity layer. forming a photoresist layer and planarizing the photoresist layer;
The method includes the steps of performing etch-back to remove the dummy gate electrode to form an opening and forming a gate metal layer, and removing the unnecessary gate metal layer and photoresist layer by a lift-off method to form a gate electrode. do.

[Effect]

The position of the n layer or the position of the upper eaves of the overlay gate electrode is determined by a dummy gate electrode made of a first insulator layer, for example, a silicon oxide layer, without using an alignment mask.
Using a second insulating layer, such as a silicon nitride layer, formed thereon, the gate electrode is formed in the self-alignment line by inverting the pattern of the oxide layer.

Therefore, the above-mentioned two alignments that were conventionally performed are no longer necessary, and it becomes possible to easily form the gate portion with high precision.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1(a), (b), (C) and (d) are schematic longitudinal cross-sectional views of a GaAs field effect transistor in the main steps of an embodiment of the present invention, and FIG. 2 is a schematic longitudinal sectional view of a GaAs field effect transistor manufactured thereby. FIG. 2 is a schematic vertical cross-sectional view showing a field effect transistor.

First, on a GaAs substrate l on which an n-type active layer 2 has been formed by silicon ion implantation, silicon oxide is deposited to a thickness of 3,000 to 4,000 layers by CVD over the entire surface, and after resist patterning, dry etching and wet etching are performed. Thus, a dummy gate electrode 3 made of a silicon oxide layer is formed as a first insulating layer at a predetermined position. Then, the entire surface is coated with a thickness of 1000~2 by plasma CVD method.
A silicon nitride layer 4 of 0.0000000000000000000000000000000000000000000000000000000000000000000000000000000000 nitride layers were formed through the silicon nitride layer 4 through the silicon nitride layer 4 by forming a layer 4 as a second insulating layer, patterning the resist pattern except for the element portion, leaving the gate portion untouched. An n-type layer 2 is formed (FIG. 1(a)).

Next, after activation as it is and resist patterning, a window is opened at a predetermined position on the n-type layer 5 of the silicon nitride layer 4, and a l1uG layer is formed as an ohmic electrode layer.
Form an e-Ni layer 6. Thereafter, a thick photoresist is applied for planarization, and exposure and beta are performed to form a photoresist layer 7 (FIG. 1(b)).

Next, the head of the dummy gate electrode 3 is exposed by etching back, and the dummy gate electrode 3 (
Wet etching only the silicon oxide (silicon oxide) to open the gate area. Then apply gate metal to a thickness of 5,000 mm over the entire surface.
Approximately 6,000 people are deposited to form the gate metal layer 8a (FIG. 1(C)).

Next, the photoresist layer 7 remaining during the etch-back and the gate metal layer 8a thereon are lifted off, and the gate electrode 8a is lifted off.
(Fig. 1(d)).

Including the above steps, as shown in Figure 2, the desired GaAs
A field effect transistor is manufactured.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to form an n-type layer on the self-line without a mask, and by using a planarization process, the position of the overlay region of the gate, which forms the T-shape of the overlay, can be determined without a mask. The gate metal can be selected, which simplifies the process and improves electrode position accuracy.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are schematic vertical cross-sectional views showing a GaAs field effect transistor in main steps of an embodiment of the present invention. FIG. 2 is a schematic longitudinal sectional view showing a GaAs field effect transistor according to an embodiment of the present invention. ■...GaAs substrate, 2...active layer, 3...dummy gate electrode, 4...silicon nitride layer, 5...n
゛-type layer 6... AuGe-Ni layer, 7... Photoresist layer, 8... Gate electrode, 8a... Gate metal layer.

Claims (1)

[Claims] 1. In a method for manufacturing a field effect transistor including a step of forming a gate electrode, the step of forming the gate electrode (8) includes: forming a semiconductor substrate (1) on which an active layer (2) is formed; A dummy gate electrode (3) made of the first insulating layer is placed at a predetermined position on the top.
forming a second insulating layer (4) on the surface thereof, and selectively implanting a predetermined impurity into the second insulating layer (4) to form a high concentration impurity layer (5); a step of forming an ohmic electrode layer (6), forming a photoresist layer (7) and planarizing it; a step of etching back and removing the dummy gate electrode to form an opening and forming a gate metal layer (8a); A method for manufacturing a field effect transistor, comprising the step of removing the unnecessary gate metal layer and the photoresist layer by a lift-off method to form a gate electrode (8).