JPH01200727A - Data transmission equipment - Google Patents
Data transmission equipmentInfo
- Publication number
- JPH01200727A JPH01200727A JP2291788A JP2291788A JPH01200727A JP H01200727 A JPH01200727 A JP H01200727A JP 2291788 A JP2291788 A JP 2291788A JP 2291788 A JP2291788 A JP 2291788A JP H01200727 A JPH01200727 A JP H01200727A
- Authority
- JP
- Japan
- Prior art keywords
- automatic equalizer
- memories
- remote side
- control signal
- data transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title claims description 14
- 230000015654 memory Effects 0.000 abstract description 16
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、変復調器および自動等化器を備えるデータ伝
送装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device including a modem and an automatic equalizer.
パルス信号によるデータの伝送には、搬送波を変調した
交流信号が一般に用いられておシ、これの受信に際して
は、伝送線路によシ生ずる振幅歪、遅延歪等の伝送歪を
補正するため、近来は自動等化器が用いられ、相手側か
ら通信の開始に先立って送られて来るトレーニング信号
によシ、自動等化器の最適なタップ係数を自動的に設定
するものとなっている。For data transmission using pulse signals, an AC signal modulated with a carrier wave is generally used.When receiving this signal, in order to correct transmission distortion such as amplitude distortion and delay distortion caused by the transmission line, recently An automatic equalizer is used, and the optimal tap coefficients of the automatic equalizer are automatically set based on a training signal sent from the other party prior to the start of communication.
第2図は、従来例の受信側を示すブロック図であシ、自
動等化器を備える復調回路1には、自動等化器のタップ
係数を記憶するメモリ2が付属しており、線路を介する
受信信号11としてトレーニング信号が与えられている
間に、復調回路1中の自動等化器が使用線路の伝送特性
に応じて自動的に最適なタップ係数を設定し、これをメ
モリ2により記憶し、これによシ等化状態を定めた後、
復調回路1が以降の受信信号を復調し、復調出力12と
して送出するものとなっている。FIG. 2 is a block diagram showing the reception side of a conventional example. A demodulation circuit 1 equipped with an automatic equalizer is attached with a memory 2 for storing the tap coefficients of the automatic equalizer, and While the training signal is being given as the received signal 11 through the demodulation circuit 1, the automatic equalizer in the demodulation circuit 1 automatically sets the optimum tap coefficient according to the transmission characteristics of the line used, and stores this in the memory 2. After determining the equalization state using this,
A demodulation circuit 1 demodulates subsequent received signals and sends them out as demodulated output 12.
しかし、タップ係数は、相手側との間の使用線路に応じ
て変化するものであシ、複数の相手側と交互にデータ伝
送を行なう場合、相手側に応じて自動等化器がその都度
タップ係数の設定を行なわねばならず、これが最適とな
る収束状態へ達するまでの所要時間は、例えば、CCI
TT V、29のセグメント3によるとき160m5e
cであシ、この間は正常な受信が不可能なため、相手側
を変更する度毎にこの収束時間を要し、全般的に伝送効
率が低下する欠点を生じている。However, the tap coefficient changes depending on the line used between the other parties, and when data is transmitted alternately with multiple parties, the automatic equalizer taps each time according to the other party. The coefficients must be set, and the time required to reach the optimal convergence state is, for example, CCI
160m5e according to segment 3 of TT V, 29
c. During this period, normal reception is impossible, so this convergence time is required each time the other party is changed, resulting in a drawback that overall transmission efficiency is reduced.
前述の課題を解決するため、本発明はつぎの手段によ多
構成するものとなっている。In order to solve the above-mentioned problems, the present invention is constructed by the following means.
すなわち、上述のデータ伝送装置において、自動等化器
のタップ係数を記憶する複数の記憶回路と、サブチャネ
ルを経由して相手側から受信した制御信号に応じ各記憶
回路中の対応するものを選択して自動等化器へ接続する
切替回路とを設けたものである。That is, in the data transmission device described above, there are a plurality of memory circuits that store the tap coefficients of the automatic equalizer, and a corresponding one of the memory circuits is selected according to a control signal received from the other party via a subchannel. and a switching circuit for connecting to an automatic equalizer.
したがって、複数の記憶回路によシ、複数の相手毎のタ
ップ係数が記憶されておシ、サブチャネルを介する相手
側からの制御信号に応じて対応する記憶回路のタップ係
数が自動等化に用いられるものとなシ、自動等化器の収
束が速やかとなる。Therefore, tap coefficients for each of a plurality of parties are stored in a plurality of memory circuits, and the tap coefficients of the corresponding memory circuits are used for automatic equalization in response to a control signal from the party via a subchannel. The automatic equalizer will converge more quickly if it is possible.
以下、実施例を示す第1図のブロック図によって本発明
の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to the block diagram of FIG. 1 showing an embodiment.
同図においては、復調回路1に対し、複数のメモリ21
〜2nが設けであると共に、これらと復調回路1との間
に切替回路3が介在しておシ、これには、サブチャネル
を経由した相手側からの制御信号13が与えられるもの
となっている。In the figure, a plurality of memories 21 are provided for the demodulation circuit 1.
~2n are provided, and a switching circuit 3 is interposed between these and the demodulation circuit 1, and a control signal 13 from the other side via the subchannel is applied to this. There is.
また、切替回路3は、相手側に個有の制御信号13に応
じ、メモリ21〜2n中の対応するものを選択し、復調
回路1中の自動等化器へ接続するものとなっておシ、メ
モリ21〜2nの各々には、複数の相手側との間の各伝
送線路毎に求められた最適なタップ係数が記憶されるた
め、再び同一の相手側との通信を行なうときには、相手
側からの制御信号によシ以前に記憶したタップ係数が用
いられるものとなシ、自動等化器の収束が直ちに行なわ
れる。Further, the switching circuit 3 selects a corresponding memory among the memories 21 to 2n in response to a control signal 13 unique to the other party, and connects it to the automatic equalizer in the demodulation circuit 1. , each of the memories 21 to 2n stores the optimal tap coefficient determined for each transmission line between multiple parties, so when communicating with the same party again, the If the previously stored tap coefficients are used by the control signals from the automatic equalizer, convergence of the automatic equalizer will occur immediately.
以上の説明によシ明らかなとおシ本発明によれば、自動
等化器のタップ係数を記憶する複数の記憶回路と、サブ
チャネルを経由して相手側から受信した制御信号に応じ
各記憶回路中の対応するものを選択して自動等化器へ接
続する切替回路とを設けたことによシ、複数の相手側と
交互に通信を行なう際、以前に記憶回路によシ記憶した
タップ係数を用いて自動等化器の収束が即応してなされ
、相手側の変更毎に生ずる収束所要時間が不要とガシ、
全般的な伝送効率が大幅に向上し、自動等化器を備える
データ伝送装置において顕著な効果が得られる。As is clear from the above description, the present invention includes a plurality of storage circuits for storing tap coefficients of an automatic equalizer, and each storage circuit in response to a control signal received from the other party via a subchannel. By providing a switching circuit that selects the corresponding one among them and connects it to the automatic equalizer, when communicating alternately with multiple parties, the tap coefficient previously stored in the memory circuit can be used. The automatic equalizer converges on the fly using
The overall transmission efficiency is greatly improved, and a remarkable effect can be obtained in a data transmission device equipped with an automatic equalizer.
第1図は本発明の実施例を示すブロック図、第2図は従
来例のブロック図である。
1・・拳・復調回路、2.21〜2n・・・・メモリ、
3・・・・切替回路、11・・・・受信信号、13・・
・・制御信号FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 1...Fist/demodulation circuit, 2.21~2n...memory,
3...Switching circuit, 11...Received signal, 13...
··Control signal
Claims (1)
動的に等化する自動等化器を備えたデータ伝送装置にお
いて、前記自動等化器のタップ係数を記憶する複数の記
憶回路と、サブチャネルを経由して相手側から受信した
制御信号に応じ前記各記憶回路中の対応するものを選択
して前記自動等化器へ接続する切替回路とを設けたこと
を特徴とするデータ伝送装置。A data transmission device including an automatic equalizer that automatically equalizes transmission distortion of the line by a signal received via the line, comprising: a plurality of storage circuits for storing tap coefficients of the automatic equalizer; A data transmission device comprising: a switching circuit that selects a corresponding one of the storage circuits and connects it to the automatic equalizer in accordance with a control signal received from the other party via a channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2291788A JPH01200727A (en) | 1988-02-04 | 1988-02-04 | Data transmission equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2291788A JPH01200727A (en) | 1988-02-04 | 1988-02-04 | Data transmission equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01200727A true JPH01200727A (en) | 1989-08-11 |
Family
ID=12095994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2291788A Pending JPH01200727A (en) | 1988-02-04 | 1988-02-04 | Data transmission equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01200727A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2017061247A1 (en) * | 2015-10-09 | 2018-07-26 | ソニー株式会社 | Bus system and communication device |
| WO2019244634A1 (en) * | 2018-06-18 | 2019-12-26 | 日本電信電話株式会社 | Signal processing device and optical receiver |
-
1988
- 1988-02-04 JP JP2291788A patent/JPH01200727A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2017061247A1 (en) * | 2015-10-09 | 2018-07-26 | ソニー株式会社 | Bus system and communication device |
| WO2019244634A1 (en) * | 2018-06-18 | 2019-12-26 | 日本電信電話株式会社 | Signal processing device and optical receiver |
| JP2019220801A (en) * | 2018-06-18 | 2019-12-26 | 日本電信電話株式会社 | Signal processor and optical receive |
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