JPH01200744A - Packet switching system - Google Patents

Abstract

PURPOSE:To concentrate a low speed packet channel with a simplified circuit and to distribute the function of a data control and a network control by connecting a subscriber's line circuit and a trunk packet transmitting circuit with a transmitting requiring line, an address line, a transmitting line and a receiving line in a bus form. CONSTITUTION:In case of a packet transmission from subscriber circuits 120-12m to a trunk packet transmitting circuit 13, when it coincides with an address sent from the circuit 13 to an address line 15, a transmitting requirement is executed through a transmitting requiring line 14 to the one clock inside of a lock line 17. When the circuit 13 responds to it, a subscriber's line circuit to send the transmitting requirement sends a packet to a transmitting line 16. Next, when the packet transmission is executed from the circuit 13, the packet sent from the circuit 13 to a receiving line 19 is received at the circuits 120-12m at the same time, and only the subscriber's line circuit of the address attached to the packet receives all the packets. Thus, the line is concentrated with a simplified circuit, and a control function is distributed.

Description

Detailed Description of the Invention Field of Application in Industry 2\-7 The present invention is used for intra-premises and office packet switching, circuit switching, hybrid switching of packet switching, etc. Below, T,
It's called A.N. ), and relates to a packet switching device for application to node devices, etc.

2. Description of the Related Art Conventionally, this type of packet switching equipment uses carrier detection multiple access collision detection (hereinafter referred to as They are configured to be able to communicate with each other by concentrating lines using the C8MA/CD (C8MA/CD) method or the talk passing method.

FIG. 3 shows the configuration of an example of a conventional packet switching device.

In FIG. 3, the signal (take) of the subscriber line 1° to 1 m, which is a low-speed packet transmission path connected to the terminal or the home termination device (hereinafter simply referred to as the terminal), is transmitted to the subscriber line circuit 2°. ~2m, trunk transmission line 4 via concentrator 3
Be sent to.

Further, the take from the four main transmission lines is distributed via the line concentrator 3 to the subscriber line circuits 2° to 2 m and the subscriber lines 1° to 1 m.

Note that take link control and network control with terminals are performed by the line concentrator 3.

FIG. 4 shows the configuration of another example of a conventional packet switching device.

In FIG. 4, data from a terminal or a terminal adapter 5° to 5 m for connecting the terminal to the network is sent to the core transmission line 4 via the core packet transmission circuit 7 in a bus-type transmission form using a coaxial cable 6. Be it.

In addition, data from the core transmission line 4 is transmitted via the core packet transmission circuit 7 and the coaxial cable 6 to the terminal terminals 5° to 5.
distributed to m.

Note that take link control and network control with the terminal are performed by the terminal actuator 5° to 5m and the basic packet transmission circuit 7.

In this way, even in the conventional packet switching device described above, the line concentrator 3, the terminal actuators 50 to 5m, or the core packet transmission circuit 7 perform take-link control.

By performing network control, a plurality of subscriber lines of 1° to 1 m and terminals can be accommodated and concentrated.

Problems to be Solved by the Invention However, in the conventional packet switching device shown in FIG. [Performance] Second, there was a problem in that the subscriber line that could be accommodated was limited to 1° to 1 m.

In addition, in the conventional packet switching device shown in FIG. 4, since the coaxial cable 6 is of a bus type transmission form, the distance between the terminal adapters 5° to 5 m and between the terminal adapters 5° to 5 m and the backbone packet transmission circuit 7 is Since transmission conflicts occur between the two, sophisticated control techniques such as C8MA and /CD systems are required to avoid conflicts, resulting in the problem that the core packet transmission circuit 7 and algorithm become complicated.

The present invention solves these conventional problems5.
-It is possible to condense and accommodate low-speed packet transmission lines into the core packet transmission line with a simple circuit, and to control data links.
The object of the present invention is to provide an excellent packet switching device capable of distributing network control functions.

Means for Solving the Problems In order to achieve the above object, the present invention separates the transmission and reception functions, and connects a plurality of subscriber line circuits and a core packet transmission circuit at multiple points to form a line concentration. It is.

Therefore, according to the present invention, it is possible to condense a packet transmission line by connecting a plurality of subscriber line circuits and the main packet transmission circuit output in a bus form using a transmission request line, an address line, a transmission line, and a reception line. Can take link control,
This has the effect that the network control function can be distributed between the subscriber line circuit and the core packet transmission circuit.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 11o1 to 11on1..., 11
m1 to 11mn are subscriber lines as low-speed packet transmission paths connected to terminals or home termination equipment (hereinafter simply referred to as terminals), and 126 to 12m are subscriber line circuits that connect one or more subscribers. Lines 11o1 to 11on,...
1'm1 to 11mn are connected.

13 is a backbone packet transmission circuit, and subscriber line circuit 12
A transmission request line 14 for transmitting transmission requests from the subscriber line circuits 12o to 12m, an address line 15 for transmitting addresses assigned to the subscriber line circuits 12o to 12o, and A transmission line 16 that sends take from the subscriber line circuit 12° to 12m, and a subscriber line circuit 12o to 12m.
They are connected by a clock line 17 and a synchronization signal line 18 for sending clock and synchronization signals to the subscriber line circuits 12o to 12m, and a reception line 19 for sending received takes to the subscriber line circuits 12o to 12m.

2o is a core transmission line connected to the core packet transmission circuit.

7・＼−7 Next, the operation of the above embodiment will be explained.

In the above embodiment, first, the subscriber line circuits 12° to 12
In the case of packet transmission from m to the core packet transmission circuit 13, a conflict of transmission requests occurs, so the following procedure is used.

First, the core packet transmission circuit 13 connects the subscriber line circuits 12o to 12 to the address line 15, as shown in FIG. 2(a).
The address 1 (1=○~m, m=127 in this example) assigned to m is sequentially transferred to the synchronization signal line 1.
8 synchronization signal (Fig. 2 (1))), the subscriber line circuits 12o to 12m receive and receive the address l, and the addresses that match the individually assigned addresses and which they wish to transmit. When a packet is present, clock line 1
A transmission request is notified to the core packet transmission circuit 13 via the transmission request line 14 within a time period of one clock length of the clock provided from 7 (FIG. 2(C)) (FIG. 2(D)).
).

When the core packet transmission circuit 13 receives a transmission request, it immediately sends out to the address line 15 all addresses that are not given to the subscriber line circuits 12o to 12m, so the transmission request is not sent. subscriber line circuits 12o to 1
2m sends packet data to the transmission line 16 (FIG. 2(e)).

When the subscriber line circuits 12o to 12m complete transmitting the packet data, the subscriber line circuit, for example 12o, immediately cancels the transmission request sent to the transmission request line 14. Packet transmission circuit 13
starts sending addresses sequentially to the address line 15 again starting from the address (i+1) of the next subscriber line circuit 121.

Note that the address is binary information expressed by the number of bits carved by the clock and the synchronization signal, the first bit is always 1, and the address is composed of 7 bits.

Next, when packet transmission is performed from the core packet transmission circuit 13, the packets sent from the core packet transmission circuit 13 to the receiving line 19 are simultaneously supplied to the subscriber line circuits 12o to 12m. 12m receives the packet and Pakeno9 \-.

By checking the address at the beginning of the packet, the user determines whether the packet is addressed to it or not.

As a result of this judgment, if the packet is not addressed to you, the data after the address field such as the information field will not be received, and only the one-person line circuit that received the packet addressed to you, for example 12o, will receive all the packets. do.

In this way, according to the embodiment described above, it is possible to eliminate transmission conflicts with a simple circuit and a small amount of wiring, and to connect multiple subscriber lines 11o1 to 11011, . . . , 11m1 to 11.
It has the advantage of being able to condense lines m.

In addition, the functions of the multiple subscriber line circuits 12o to 12m and the backbone packet transmission line 13 can be clearly separated, and data link control and network control can be distributed to multiple subscriber line circuits. have

Effects of the Invention As is clear from the above embodiments, the present invention has a plurality of forces]
] The main line circuit and the core packet transmission line are separated into transmitting and receiving sections and connected at multiple points, or 108.

First, since an address line and a transmission request line are provided, transmission conflicts can be eliminated with a simple circuit and a small amount of wiring, and a plurality of low-speed packet transmission lines can be concentrated.

Further, the functions of the plurality of subscriber line circuits and the backbone packet transmission path can be clearly separated, and data link control and network control can be distributed to the plurality of subscriber line circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of a packet switching device according to an embodiment of the present invention, FIG. 2 is a timing chart showing main signals of the packet switching device of FIG. 1, and FIGS. 3 and 4 are conventional packet switching devices. FIG. 2 is a configuration block diagram of the device. 11o1 to 11oo, ..., 11m1 to 11nln subscriber line, 12o to 12n1... subscriber line circuit, 13 core packet transmission circuit, 14-transmission request line, 15 address line, 16 transmission line, 19-reception line, 20 core transmission lines.

Claims (1)

[Claims] A plurality of subscriber line circuits to which at least one or more low-speed packet transmission lines are connected, and a backbone packet transmission circuit to which a backbone transmission line is connected are provided, and the plurality of subscriber line circuits and the backbone packet transmission circuit are provided. from the plurality of subscriber line circuits to the basic packet transmission circuit, a transmission request line for sending a transmission request, a transmission line for sending a signal, and from the basic packet transmission circuit to the plurality of subscriber line circuits, The addresses assigned to the plurality of subscriber line circuits are sequentially transmitted, and when a transmission request is received from the subscriber line circuit corresponding to the address, an address line is used to transmit an address other than the above address, and the received signal is transmitted to the address line. A packet switching device connected to the sending and receiving lines.