JPH01205683A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To eliminate danger to destroy an A/D converting part by an excess current by inputting output, the content of which is the subtracted value of the output corresponding to a black reference picture element, to the A/D converting part in a case when the subtracted value ot the output corresponding to the black reference picture element is outputted and inputting the output of a determined range voltage output means in the other cases. CONSTITUTION:Switches 28 and 29 are switched so that the subtracted value of the output corresponding to the black reference picture element can be inputted to an A/D converting part 15 when a subtracting means 26 outputs the subtracted value of the output corresponding to the black reference picture element from the output corresponding to a use picture element. On the other hand, the switches 28 and 29 are switched so that the output of a determined range voltage means 27 can be inputted to the A/D converting part 15 when the subtracting means 26 does not output the subtracted value of the output corresponding to the black reference picture element from the output corresponding to the use picture element, namely, the subtracting means 26 outputs the subtracted value of the black reference picture element from the output of nonuse picture element. Thus, a signal to exceed its dynamic range is never inputted to the A/D converting part 15, and the dager to destroy the A/D converting part 15 is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a solid-state imaging device used in an automatic focus detection device of a camera or the like.

<Prior Art> Conventionally, in this type of solid-state imaging device, a part of the photoelectric conversion unit corresponds to the pixel used, and another part of the photoelectric conversion unit corresponds to the black reference pixel by shielding light, and the above-mentioned The electric charge from the photoelectric conversion section is accumulated in the accumulation section, and the output corresponding to the black reference pixel output from the accumulation section is subtracted from the output corresponding to the used pixel output from the accumulation section using a subtraction means to calculate the dark current. There is a device which is designed to obtain a photoelectric output that does not include the component (JP-A-59-154880).

By the way, in a solid-state imaging device used for an automatic focus detection device, etc., there are used pixels that are used for the system and unused pixels that are unnecessary for the system, and a photoelectric conversion unit is installed in the unused pixels that are unnecessary for the system. It has been removed and other circuits have been inserted.

By the way, if the output corresponding to the black reference pixel is always subtracted by the subtraction means as in the conventional solid-state imaging device described above, when the output corresponding to the black reference pixel is subtracted from the output of the unused pixel, the subtraction The value becomes a negative output, and if this negative output is input to the A/D converter, the input dynamic range will be exceeded and the A/D converter may be destroyed.

Furthermore, when the subtraction means subtracts the input signal corresponding to the black reference pixel from the pixel input after reading out the pixel signal from the storage section, a negative subtraction value is obtained, resulting in overcompensation.
/D converter may be destroyed.

Therefore, an object of the present invention is to be able to always input a signal within the dynamic range to an A/D converter connected to a solid-state imaging device, and to avoid the risk of destroying the A/D converter due to overcurrent. The purpose of the present invention is to provide a solid-state imaging device.

Means for Solving the Problems> In order to achieve the above object, the solid-state imaging device of the present invention has the following features:
As illustrated in Figures 1.2 and 11.13, a plurality of photoelectric conversion units (P
D), a storage section (ST) that stores charges from each photoelectric conversion section (PD), and a storage section (ST) that corresponds to the pixel used.
); a subtracting means (26) for at least subtracting the output of the storage section (ST) corresponding to the black reference pixel from the output of the storage section (ST); and a fixed range voltage output means (26) for outputting a voltage limited to a certain range.
27), and when the subtraction means (26) outputs a subtracted value of the output of the storage section (ST) corresponding to the black reference pixel from the output of the storage section (ST) corresponding to the pixel in use. This subtracted value is manually input to the A/D converter (15), while the subtraction means (26) calculates the output of the storage section (ST) corresponding to the black reference pixel from the output of the storage section (ST) corresponding to the pixel used. a switch (28, 29) for manually inputting the output of the fixed range voltage output means (27) to the A/D converter (15) when the subtracted value of the output of ST) is not output. It is characterized by

Further, the fixed range voltage output means is connected to a resistor dividing circuit (27).
It is preferable to provide a switch (31) between the resistance divider circuit (27) and the power supply.

Function> A part of the photoelectric conversion unit (PD) outputs a signal corresponding to the used pixel, and the other part, which is shielded from light, outputs a signal corresponding to the black reference pixel. Charges from each photoelectric conversion section are accumulated in a storage section (ST). On the other hand, the subtracting means (26) subtracts the output of the storage section (ST) corresponding to the black reference pixel from the output of the storage section (ST) corresponding to the used pixel. Also,
The fixed range voltage output means (27) outputs a voltage limited to a fixed range. The switches (28, 29) are configured to input the subtracted value to the A/D converter when the subtracting means outputs a subtracted value of the output corresponding to the black reference pixel from the output corresponding to the used pixel. can be switched to on the other hand,
When the subtraction means does not output a subtracted value of the output corresponding to the black reference pixel from the output corresponding to the used pixel, that is, for example, when it outputs the subtracted value of the black reference pixel from the output of the unused pixel. , the above switches (28, 29
) is switched so that the output of the fixed range voltage means is manually input to the A/D converter. Therefore, a signal exceeding the range will not be input to the A/D converter, and
There is no risk of destroying the A/D converter. That is, there is no overcompensation by subtraction of the output corresponding to the black reference pixel, and input is always within the human power range, so there is no risk of destroying the A/D converter due to overcurrent.

In addition, a resistance divider circuit (27) which is a fixed range voltage output means
Power consumption can be reduced by turning off the switch (31) between the power source and the power source when constant voltage is not required.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

First, a first example will be described. FIG. 1 shows the configuration of an image sensor (13) manufactured as a COD.

(1) is a photodiode array consisting of a plurality of photodiodes (PD) as photoelectric conversion means that generate charges according to the amount of incident light, and (ST) is an accumulation section that accumulates charges generated by the photodiodes (PD). , (B.G.
) is a barrier gate consisting of a field effect transistor (hereinafter referred to as FET), which is a gate provided between the photodiode (PD) and the storage section (ST), and this barrier gate (I3G) is connected to the voltage When voltage is applied, the photodiode (PD) and storage section (ST) are connected to allow the charge generated in the photodiode (PD) to flow into the storage section (ST), while when no voltage is applied, the photodiode (FD) and storage section (ST) are connected. (ST) and stops the charge generated in the photodiode (FD) from flowing into the storage section (ST). Also, (RG) transfers charge from left to right in the drawing by two-phase drive. The transfer register (SH) is the storage unit (
This is a transfer gate made of PET, which is a gate provided between the transfer register (RG) and the transfer register (RG). This transfer gate (SH) connects the storage section (ST) and the transfer renoster (RG) when a voltage is applied, and transfers the charge accumulated in the storage section (ST) to the transfer register (RG), while applying the voltage. When no voltage is applied, the storage section (ST) and transfer register (R
G) to prevent charges accumulated in the storage section (ST) from flowing into the transfer register (RG). Also, (R
GICC) is an integral clear gate consisting of a gate or FET. This integral clear gate (RGICG) is
When voltage is applied, the transfer register (RG) and overflow drain (ODI) are connected, and before integration, unnecessary charges in the photodiode (PD) and storage section (ST) of each pixel are transferred from the transfer register (RG) to the overflow drain (ODI). ODI). The overflow drain (ODI) is connected to the power supply voltage VDD and has the lowest potential.

On the other hand, an overflow gate (OG) is provided between the photodiode (PD) and the overflow drain (OD2).
No voltage is applied to G), and it is always fixed at a potential lower than the potential of the barrier gate (BG) when no voltage is applied. The charge of each pixel transferred to the transfer register (1"tG) is sequentially transferred to the capacitor (8-1) from the right side in the drawing by the transfer lock φ1.φ.The capacitor (8-1) Prior to being transferred,
Charging is reset to the power supply voltage by the 0SRS signal applied to the gate of F'ET (8-3). Thereafter, the potential of the capacitor (8-1) decreases from the charging voltage by the amount of transferred charge. The voltage across the terminals of this capacitor (8-1) is taken out as the O8 signal by the buffer (8"-2). Note that (8-1) has been described here as a capacitor for convenience of explanation, or as a PN of a diode. This capacitor can be replaced with a junction, and when the circuit is integrated, this capacitor is manufactured as a diode.Hereinafter, when the capacitor is referred to as a capacitor, the same applies.

A light-shielding AC film (1-1) is provided on the plurality of photodiodes (PD) at the ends of the photodiode array (1) in order to take out a black reference pixel output, which will be described later.

The photodiode array (1) detects pixels necessary for the automatic focus detection system using blocks on both sides except for the central area.
) corresponds to unused pixels that are unnecessary for the automatic focus detection system. For this reason, the central photodiode (PD) of the photodiode array (1) corresponding to the unused pixel is removed, and a photodiode (9) for brightness monitoring (to be described later) is installed in this removed portion for output processing. A part of the circuit is inserted (see Figure 21).

Further, in order to control the integration time of the image sensor (13), a brightness monitoring photodiode (9) is provided as brightness monitoring means for monitoring the amount of light incident on the photodiode (PD).

The brightness monitor photodiode (9) has an elongated shape because it is formed across two blocks on both sides of the photodiode array (1) that detects pixels necessary for the automatic focus detection system. In addition, this brightness monitoring photodiode (9) is configured so as not to monitor the amount of light irradiated to the area corresponding to the unused pixel.
The portions corresponding to the unused pixels are shielded from light by an Ag film (9-1). In this way, the brightness monitor board (9) is arranged with the alignment direction of the photodiode array (+) as the longitudinal direction, and extends over the two blocks at both ends of the photodiode array (+).
At the same time as IM is created, the portion corresponding to unused pixels is Ag
Since it is covered with a film (9-1), it is possible to accurately monitor the average output level of the portion corresponding to the pixel used. A part of the circuit for output processing of the brightness monitoring photodiode (9) is inserted in the center of the photodiode array (1) from which the photodiode (PD) has been removed, as shown in FIG.

As mentioned above, the brightness monitoring photodiode (9) has an elongated shape, and if its length is Q, and the output is taken out from one end, generally the length g and the response time τ
The relationship τoc Q 2 holds true, and the longer the length Q, the more rapidly the responsiveness deteriorates. Therefore, in order to prevent the responsiveness from deteriorating, the output is extracted from the extraction electrode near the center of the brightness monitoring photodiode (9). Therefore, the response time is 1/4 compared to the case where a contact is provided at the end of the photodiode (9), as shown in the following equation.

In this way, since the extraction electrode is provided near the center and the response of the brightness monitoring photodiode (9) is fast, even if the integration time is determined based on the output of the brightness monitoring photodiode (9), it will not be excessive. Appropriate integration can be performed without performing excessive integration that stores charges in the storage section (ST).

A capacitor (IO-1), which is a storage means, is connected to the brightness monitoring photodiode (9), and prior to integration of the image sensor (13), an FET (I O
-3) When ACCI' (S signal is applied to the gate of
The capacitor (10-1) is charged to the power supply voltage VDD. After the AGcR9 signal is removed, the potential at the capacitor (10-1) drops due to charges generated in response to light irradiation. This potential is applied to a buffer (10
-2) is output as an AGCO8 signal.

The compensation diode (11) is provided to remove the dark output of the brightness monitor photodiode (9), and a light-shielding ρ film (II-1) is provided on top of the compensation diode (11). This compensation diode (11) is designed to obtain the same amount of output as the dark output of the brightness monitor photodiode (9), but if it has the same structure as the brightness monitor photodiode (9). requires the same area as the brightness monitoring photodiode (9), resulting in an increase in depth size. Therefore, as shown in FIG. 7(a), the compensating diode (II) consists of a large number of N-type parts separated from each other and arranged at regular intervals, and these are made into P-type parts. By embedding it in the dark area, the length (peripheral length) La of the PN junction on the surface, which is the source of the dark output, is increased, and the same amount of dark output can be achieved with a smaller size than the brightness monitor photodiode (9). It is designed to provide the following.

The compensation diode (II) is connected to the capacitor (12-1
). This capacitor (+2-1) is connected to the FET (12-3) prior to integration of the image sensor (13).
) is charged to the power supply voltage VDD by the AGCR9 signal applied to the gate. However, after the AGCnS signal is removed, the potential of the capacitor (12-1) gradually decreases due to the dark output charge of the compensation guide (11). This potential is output as a DOS signal via a buffer (+2-3). This concludes the description of the configuration of the image sensor (13).

Next, the overall hardware configuration will be explained along the block diagram of FIG. (+4) in the middle of FIG. 2 is a microcomputer (μCom) which is an arithmetic control means for controlling the drive of the image sensor (13). Image sensor control section (16) of this microcomputer (14)
are the output of two signals MD, , MD, for switching the four modes of the image sensor (13, which will be described later), and two signals NBI, N for providing the operation timing.
At the same time, an ADT signal is inputted from the I10 buffer (22), which is the logical sum of a TINT signal indicating whether or not integration has been completed, and an ADS signal indicating the start of A/D conversion of the image sensor output. Also, gain information GL.

The G3 signal is input using the NB, , NB, signal line.

The circuit on the left side of the microcomputer (14) is
It is constructed on a 1-chip IC. Among these, the above 1
The 10 buffer (22) has the following functions. That is,
A function of ORing the above TINT signal and ADS signal and outputting it to the microcomputer (14) as an ADT signal, switching the input/output of the signal line of the NB, NB, signal and NB when inputting.

The NB and G3 signals are input from the microcomputer (14), and when output, the Gl and G3 signals are input to the microcomputer (14).
14), the signal level of the microcomputer (14), the frequency dividing circuit (+9), the integration time control section (20), the signal processing timing generation section (21), and the transfer lock generation section (30). ), etc., has an interface function with the signal level in the circuit.

On the other hand, the mode selection circuit (23) selects M D 1. M
Decodes the D2 signal and selects one of the following four modes.
This circuit selects two modes. MD, -“L”.

When M D t = “L”, the mode selection circuit (23)
sets only the INl signal to "I" and selects the INI mode. The INI mode is a mode for initializing the image sensor (+3). MD, = “shi”.

In the case of MD, -“■]”, the mode selection circuit (23)
Only the NT signal is set to "H" to select the INT mode.

The INT mode is a mode in which the image sensor (13) performs integration. If MD, - “H”, MD, = “H”,
The mode selection circuit (23) sets only the DDl signal to "H" and selects the DDI mode. The DDI mode is a mode in which readout of the image sensor (13) is started, and is also a mode in which zumble hold of black reference pixels, which will be described later, is performed using the NB, , NBt signals. MD,=″H″
, when M D t = “L”, the mode selection circuit (2
3) sets only the DD2 signal to "H" and selects the DD2 mode. The DD2 mode is a mode in which the image sensor (13) is read and the read and processed output of the image sensor (13) is sent to the A/D converter (15) of the microcomputer (14). . The operation and functions of each mode will be described later.

The above frequency dividing circuit (19) is a microcomputer (14)
The reference clock CP generated by the clock generator (+8) of
The image sensor (13) transfer lock φ3. The clock φ that is the source of φ. At the same time,
Integral time control section (20) and signal processing timing generation section (
21) clock φ. A timing clock φ is generated for synchronization with the

The above clock φ. is sent to the transfer lock generation section (30), where S sent from the integral time control section (20)
H double signal RGI CG double signal clock φ.

Therefore, the clock φ3. φ, and serves as a transfer lock for the image sensor (13). The integral time control section (20) receives a timing signal N transmitted from the microcomputer (14) in INI mode and TNT mode.
Based on the signals B, , NB, the Accrts signal, the BG multiplied signal 5I-1 signal, and the RGTCG signal are generated in synchronization with the clock φ sent from the frequency divider circuit (19), and the integration start operation is performed. Each of the above signals is applied to each part of the image sensor (+3) shown in FIG. The integration time control unit (20) also receives an integration completion signal VFLG from the brightness determination circuit (24), which is a subtraction means, which becomes "L" - "H" when the integration of the image sensor (13) becomes appropriate; Alternatively, a BG multiplied signal is generated by the timing signals NB, NB, which are transmitted when the DDl signal from the mode selection circuit (23) is "H", and the integration is completed.

Furthermore, this integration time control section (20) is configured so that the DDI signal is “
T(", the timing signal NB,.

NB generates a signal times SH and performs an operation to start reading the output from the storage section ('ST). At this time, a signal for obtaining luminance information, which will be described later, an SH multiplied signal, and φa, φb, φC2φd signals are transmitted to the luminance determination circuit (24). The brightness determination circuit (24) monitors the advance irradiation on the image sensor (13) using the AGCOS signal and DOS signal sent from the image sensor (I3), and when it is determined that the integral or appropriate level has been reached. ,V
A function to invert the FLG signal and convert the integration to VFL at low brightness.
If the G signal is an inverse signal inverter, determine the level of integration,
It has a function of outputting Gl and G3 signals for switching the gain of the image sensor (13) according to the level.

AGC differential amplifier circuit (25) is an image sensor (13)
This circuit amplifies the output signal O8 sent from.

In this AGC differential amplifier circuit (25), the F'ET (
8-3) samples and holds the potential O8 immediately after the capacitor (8-1) is charged by the R3S/H signal sent from the signal processing timing generation section (21), and then transfers this potential O8 and uses it according to the lock. Capacitor (
The difference between the potential O8 of the capacitor (8-1) that has dropped due to the generated charge of each pixel transferred to 8-1) is taken, and this is amplified, and the OB subtraction AGC difference, which is a subtraction means, is taken as a signal Vos'. It is output to the dynamic amplifier circuit (26).

The amplification cane of the OB subtraction AGC differential amplifier circuit (26) is switched by the G3 signal output from the brightness determination circuit (24). The AGC amplifier circuit (26) performs differential amplification between the output of the black reference pixel and the output of the normal pixel without Aρ light shielding, that is, the effective pixel, and the output V
Sample and hold of os' is performed. Since the photodiode (FD) always has an output in the dark, the pixel detected by the photodiode (PD) with AC light shielding is used as the black reference pixel and the reference pixel for the dark output. The value obtained by subtracting the black reference pixel component is the output of the image sensor (13). O above
Since the output Vos' from the AGC differential amplifier circuit (25) is repeatedly input to the B subtraction AGC amplifier circuit (26) in synchronization with the transfer lock, the B subtraction AGC amplifier circuit (26) receives the OSS/ Sample and hold the level of the signal output Vas' of the HSS/upstream and effective pixels,
Also, O sent from the signal processing timing generator (21)
Due to the BS/H signal, while the black reference pixel is being output, its output V
Sample and hold os'.

The OB subtraction AGC amplifier circuit (26) subtracts the sampled and held output level Vos' of the valid pixel from the sampled and held signal output level Vos' of the effective pixel,
Furthermore, the signal is multiplied by a gain that is switched by the G3 signal output from the brightness determination circuit (24), and is output as a signal Vos below the analog reference voltage Vref.

The temperature detection section (27), which is a fixed range voltage output means,
Temperature is detected by the resistance divider circuit shown in Figure 3. This resistor divider circuit (27) includes a diffused resistor (32) formed by diffusion and a resistor (33) formed of poly-silicon (Poly-Si), which are designed to have equal resistance values at room temperature. There is. Each resistor (32), (
33) have different temperature coefficients, the output VTMP output from their connection point via the buffer (34) is V
It depends on the temperature around ref/2. In addition, the analog switch (31) is DD in DD2 mode.
By turning off the analog switch (31), the current consumption is reduced. On the other hand, the analog switch (28) shown in FIG. This turns on the output Vou in the DD2 mode.
The signal Vos is output as the output t, and the signal VTMP is output as the output Vout in modes other than DD2 mode. The signal Vout is input to the A/D converter (15) in the microcomputer (14), where the analog reference voltage V
A/D conversion of the analog output on the lower voltage side than ref
It starts with a DT signal and converts it to digital data.

In this way, when the analog reference voltage (28, 29) is switched and the OB subtraction AGC differential amplifier circuit (26) outputs the signal Vos corresponding to the pixel used, the signal is sent to the A/D converter. (15), while in other cases, the voltage VTM within a certain range is input from the temperature detection section (27).
Since P is input manually to the A/D converter (15), the negative output generated by subtracting the output corresponding to the black reference pixel from the output corresponding to the unused pixel from the OB subtraction AGC differential amplifier circuit (26), Even if a negative output is generated by subtracting the output of the black reference pixel from the output of the used pixel after pixel reading is completed, these are not manually input to the A/D converter (15), and the temperature detector From (27), the voltage V TMP within a certain range is input to the A/D converter (5). Therefore, the A/D conversion m(15) does not exceed the human-powered dynamic range, and there is no risk of damage.

This concludes the explanation of the hardware configuration.

Next, the operation of the image sensor (13) described in 1F7 in each mode will be explained in detail.

First, the initialization mode will be explained.

The microcomputer (14) is MD I = “L”.

When MD2-“L” is output, the mode selection circuit (23)
In this case, only the INI signal is set to “I”, and the integral time control 11 (
20) is notified that it is in the initialization mode (I!l mode). INr mode uses image sensor (13
) is a mode for discharging unnecessary charges from the image sensor (13) immediately after the power is turned on. Image sensor (
After the power is turned on, I3) is a photodiode (PD), which is a bottomless well, a storage section C3T), and a transfer register (R
G) has accumulated unnecessary charge, and it is necessary to quickly discharge this charge and start up the image sensor (13) so that it can be used. Therefore, in order to quickly discharge unnecessary charges, the INr mode was set, and the potential structure of the image sensor (13) was changed to the structure shown in FIG. 3.

Hereinafter, explanation will be given along with the potential diagram of FIG. 3 and the time chart of FIG. 4. From the left in FIG. 3(a), an overflow drain (OD 2 ), an overflow gate (OG), and a photodiode (PD).

Barrier gate (BG), storage section (ST), transfer game 1-
(SH), transfer register (RG), integral clear gate (
RG r CG), over 7C7-drain (ODl
). Barrier gate (BG), transport game 1-
(SH), each gate of the integral clear gate (RGICG), and the transfer register (RG) (φ1 is applied to the transfer register (RG)).
As shown in b), PD>EC>ST>SH>RG>R
The potential is designed so that G I CG > OD +, and the photodiode (PD), storage section (ST
), unnecessary charges in the transfer register (RG) are discharged to the overflow drain (ODl) at this time. This operation will be explained along the time chart.

The state in FIG. 4(a) corresponds to FIG. 3(a).

At this time, Ni2. In the state of = "L", NB, = "L", no voltage is applied to each gate of the barrier gate (BG), transfer gate (SI-i), and integral clear gate (RG IcG). Also a photodiode (PD).

Unnecessary charges are accumulated in each section of the storage section (ST) and transfer register (I'tG). NB,,NB2 are both "L"
In this case, the integral time control 1 (20) that controls the image sensor (13) does not perform any operation on the image sensor (I3).

The microcomputer (14) reads N B +-“I(”
.

When NB2-“L” is output, the integral time control section (20)
is the clock φ sent from the frequency dividing circuit (19). In synchronization with
.

Connect BG-“H” and RGICG-“H” to the image sensor (
13). Furthermore, S L(signal, R(, IC
C: The signal is also sent to the transfer lock generation unit (30),
The transfer lock generation unit (30) transfers the OR output of the SI (signal and clock φ) and sets it as lock φ1, and also outputs the RGI
CG signal and φ. Transfers the Noah output of and locks φ.

In the case of SH-“H” and RGICG-“■4”, the transfer lock to the image sensor (13) is stopped in the state of φ, -“I]”, φ, = “L”. There is. And the image sensor (13) is SH, BG, RGI C
As shown in FIG. 3(b), the G, φ, and φ2 signals cause the photodiode (PD), storage section (ST),
Discharge unnecessary charges from the transfer register (RG).

The microcomputer (14) then reads N B + −
After outputting “11”, NB, -“H”, NB, -“L”
”.

Outputs NB2="H". In response to this, the integral time control section (20) sets the clock φ. and returns the SH double signal and BG double signal to “L” (Fig. 3 (C), Fig. 4 (C)
)). On the other hand, in the transfer lock generating section (30), the S H signal returns to "OFF", so that the transfer lock φ starts to move, and the transfer lock φ is at "L".

At this time, the potential difference between the transfer register (RG) and the overflow drain (ODI) increases, promoting the discharge of unnecessary charges from the transfer register (RG), and discharging them completely to the overflow drain (ODI) (third stage). Figure (d), Figure 4 (d)). Also, at this time, since the transfer lock φ2 remains stopped at "L", another transfer register (RG) adjacent to the above transfer register (RG) to which the transfer lock φ2 is applied is connected to the above register (RG). ) no unnecessary charges flow into it.

After the timer measures that the predetermined time has elapsed, the microcomputer (14) returns both NB and NB2 to "OFF". The integral time control section (20) thereby controls φ0
In synchronization with this, the RG I CG double signal is set to "L". Then, the voltage applied to the RGICG terminal of the image sensor (13) becomes zero, and the integral clear gate (RGICG) becomes zero.
CG) closes. At the same time, the transfer lock generation section (
30), when the RGICG signal becomes “L”, the transfer lock φ2 starts to move (Fig. 3(e), Fig. 4(
e)). This completes the I-cycle of unnecessary charge discharge operation.

Normally, when initializing the image sensor (13), the above-described unnecessary charge discharge operation is repeated several cycles, and then the initialization mode is ended.

In the present invention, the structure in which an integral clear gate (RGrCG) is connected to each register (RG) eliminates the need to discharge unnecessary charge from each register (RG) by transferring it from the register (RG). It is possible to shorten the time for one cycle of the unnecessary charge discharge operation, and to shorten the time allocated to the initialization mode.

Next, the second mode, the integral mode, will be explained.

Microcomputer (+4) is MD +-“L”
.

When MDt-“H” is output, the mode selection circuit (23)
In this case, only the INT signal is set to “H”, and the integration time control section (20
) to notify that it is in integration mode (TNT mode). In the INT mode, the image sensor (13) starts integrating and ends the integration during high brightness.

The operation will be explained along with FIGS. 5 and 6. The integration starting operation is exactly the same as the unnecessary charge discharge operation during initialization, except for the BG multiplication signal. BG double signal NB, = “H”
, NB, - After the microcomputer (14) outputs "L", the integral time control section (20) outputs φ. (In the figure, this is the timing of the rise of φ1) and is raised to "T("). This is the same as in the IN+ mode. However, the microcomputer (14) is NB, -
When outputting “L”, NB, -“I”, in INI mode, the BG double signal “I” is synchronized with φ. and returns to the BG double signal “S”, but in INT mode, the BG double signal “I]” The BG multiplied signal becomes "L" at the end of integration, which will be described later.

At the time of Fig. 5(C) and Fig. 6(c), the transfer gate (SH
) becomes zero, the transfer gate )(Sl() returns to a higher potential than the photodiode (PD), storage section (ST), and overflow gate (OG),
From this point on, the charges generated in the photodiode (PD) flow into the storage section (ST) and begin to be accumulated in the storage section (ST), and integration begins in the image sensor (13).

On the other hand, the time point at which the integration ends is monitored by the output of the brightness monitoring photodiode (9). The operation of the brightness determination circuit (24) will be explained below, and the operation of completing the integration will be explained.

The integration time control unit (20) transmits the AGCR9 signal to the image sensor (13) at the same timing as the SH multiplication signal at the start of integration.
). As shown in FIG. 1, the AGCR9 signal is applied to a FET (10
-3) and the FET (+) connected to the capacitor (12-1) connected to the compensation diode (11)
2-3) is applied to the gate. By applying the AGCR9 signal, the capacitor (10-1)
(12-1) is charged to approximately the power supply voltage VDD. S.H.
When the AGCR9 signal becomes L'' at the same timing as the signal, the power supply is cut off, and from this point on, the brightness monitoring photodiode (9) generates a charge according to the amount of light irradiated, and the capacitor connected to it The potential of (10-[) begins to drop according to the generated charge.On the other hand, the compensation diode (11) generates a charge due to its dark output, and the capacitor (12-1) connected to it The potential begins to drop in accordance with the charge generated from the buffers (10-2) and (12-2).
The brightness determination circuit (24) shown in the figure is outputted to the analog circuit shown in FIG. In Fig. 8, the AGCO9 signal is input to the positive input of an operational amplifier (hereinafter referred to as an operational amplifier. It is output from the operational amplifier (43). The output VB of the operational amplifier (43) is expressed by the following formula.

V,,=Vrer-(DOS-AGCOS) This output V
43 is one comparator (45) which is a brightness determination means
is input to the negative input of

On the other hand, the positive human power of the comparator (45) is based on Q.
F'ET (46°4) in voltage generation circuit (RVC) IC
A constant voltage generated by resistance division according to 7.4 B, 49) is supplied. During the integration, only φd is "I", the FET (49) is turned on, and the constant voltage supplied is V, = (Vrer-Vth). The output of the comparator (45) is “H” when V43<V49.
”.In other words, Vref-(DOS-AGCOS)<Vre"-Vth
When DOS-AGCOS>Vth, it becomes "I-1".

(DOS-AGCOS) indicates a voltage dropped by light irradiation from the brightness monitoring photodiode (9) (the dark output component is compensated by the output of the compensation diode (II)). Immediately after the start of integration, the amount of light irradiated to the brightness monitor photodiode (9) is insufficient, and DOS-
AGCOS is 0, and the output of the comparator (45) (
vr;"r,c) is set to "L'. During the integration (D
At the point when OS-AGCOS) becomes larger than the voltage of vth, the integration for the image sensor (!3) becomes appropriate, and the output (VFLC) of the comparator (45) becomes "■7"
to "H". As shown in the time chart of FIG. 6, the integral time control section (20) sets the BG multiplied signal to "L" when the output (VFLG) of the comparator (45) is inverted. When the BG double signal becomes "L", the potential of the barrier gate (BG) becomes larger than the potential of the photodiode (PD), as shown in Figure 5(e), and the charge generated in the photodiode (PD) increases. It prevents the flow into the storage section (ST) and prevents the flow into the storage section (ST).
The charges accumulated in the V F L G signal are “I
]", that is, when the 100 signal becomes "L", it is held and the integration ends.The charge generated after the end of the integration is accumulated in the photodiode (PD), and even if the accumulation progresses, as shown in Fig. 5(e) As shown in FIG. 2, it crosses the overflow gate (OG), which has a lower potential than the barrier gate (BG), and is discharged to the overflow train (OD2), so it does not flow into the storage m (ST).

Further, the integration time control unit (20) sets the BG multiplied signal to "L" and at the same time sets the TINT signal to "L", and notifies the microcomputer (14) of the inversion of the INT signal via the ADT terminal. This concludes the explanation of the integration start operation in the integration mode and the integration end operation during high brightness.

Next, the third mode, data read mode I (DDI
mote).

The microcomputer (14) is MD, = “H”.

When MD2-“H” is output, the mode selection circuit (23)
In this case, only the DD+ signal is set to “11”, and the integral time control section (2
0) to notify that it is in DD+ mode. The DD [mode is a mode in which the integration is completed at low brightness and the reading of each pixel data of the image sensor (13) is started.

First, the integration termination operation at low luminance will be explained based on the time chart of FIG. 22. When the subject brightness is low, it may take a long time until the brightness determination circuit (24) determines that the appropriate integration time has been reached. If integration is performed for a long time, the dark output increases, leading to deterioration of the S/N ratio. Furthermore, an extremely long integration time is inconvenient from a system perspective.

For example, when used in a focus detection device for a camera, the focus detection cycle becomes long, resulting in the inconvenience that the focus detection cannot follow the movement of the subject. Therefore, the longest integration time allowable within the microcomputer (14) is set in advance, and if the TINT signal output to the ADT terminal has not been inverted even after this time, the M
Output D, -“I1”0MD2-“I-(”, DDI
mode, and completes the integration in DD1 mode. In the DDI mode, the integral time control section (20)
, -“H”.

N [3, - “L” signal is sent to the microcomputer (1
4), the BG double signal is immediately set to "L". As a result, as in the previous case, the potential of the barrier gate (BG) shown in Figure 1 becomes higher than the photodiode (PD), and the charge generated in the photodiode (PD) flows into the storage section (ST). stops and the integration ends (
Figure 22).

Next, the operation to start reading out each pixel data of the image sensor (13) will be explained. Regardless of whether the brightness is low or high, the microcomputer (14
) outputs NB, -“I”, NB, -“L”,
The integral time control section (20) has a transfer lock φ. sync to,
Transfer lock φ. S I-T at the timing of “I4”
Generate a signal pulse (Figure 6 or Figure 22). As a result, as shown in FIGS. 5(f) and (g), the SH agate pulse voltage of the image sensor (I3) is applied, and the signal charges of each pixel accumulated in each accumulation section (ST) are Transferred to transfer register (RG). After that, transfer lock φ9. The signal charge of each pixel is transferred and read out by φ2. The microcomputer (14) transfers the signal charges accumulated in each accumulation section (ST) to the transfer register (RG) by NB, = "TR",
This is performed when NB2-"L" is output, and at this time, it is necessary that the transfer register (RG) returns from the unsteady state after the start of integration and is in a steady state.

In a steady state, each transfer register (RG) has a dark charge of 23
It is accumulated as shown in the figure. This dark charge is the sum of the dark charge generated in the potential well of each transfer register (RG) and the dark charge of the previous stage register that is sequentially transferred. At the start of integration, the integral clear gate (RGIC
A voltage is applied to the gate terminal of the transfer register (RG).
) and overflow dreno (OD+) is turned on, and the transfer register (RGICG) is turned on.
All dark charges in G) have been cleared. After the integral clear gate (RGICG) turns off, transfer lock φ1
Every time h monthly cycles pass, the dark charge in the transfer register (rtG) reaches a steady state starting from the left side of FIG. 23.

It takes a time equal to the number of pixels (N) x one transfer lock cycle (T) until all transfer registers (RG) return to a steady state.

When the S H pulse is generated in an unsteady state, the dark charge component of the transfer register (RG) in the charge taken out as an output may be in an unsteady state depending on the pixel, so a correct signal cannot be taken out. Therefore, the SH pulse is generated at least when the RGICG signal changes from “I4” to “L”.
”, then the number of pixels × transfer lock I period (N
XT).

At high brightness, integration is often completed within one cycle (NxT), but since the integration is terminated by closing the barrier gate (BG), It is possible to make the occurrence wait.

Next, regarding the processing of the read pixel output, FIG.
This will be explained below with reference to FIG.

The signal charge of each pixel of the image sensor (13) is φ1−
At the timing of "L", φ, -"H", it is transferred to the capacitor (8-1) shown in FIG. In the signal processing timing generation section (21), prior to the transfer of this signal charge, as shown in FIG.
A 09RS signal pulse is generated at the timing of , and this pulse is applied to the gate of the FET (8-3) shown in Fig. 1.
The capacitor (8-1) is charged to approximately the power supply voltage and reset. φ1="Lo.

When the signal charge is transferred at the time when φ becomes -“H”, the voltage of this capacitor (8-1) decreases due to the signal charge, and the output O8 of the image sensor (13) becomes the 12th
The output is as shown in the figure. AGC differential amplifier circuit (
25), the voltage level at the time of reset is determined by the R6S/H signal sent from the signal processing timing generator (21) by the sample and hold circuit consisting of the FET (52), capacitor (53), and buffer (51) shown in Figure 11. According to
It is stored and input to the plus input of the operational amplifier (54).

On the other hand, the O8 signal is input to the negative input of the operational amplifier (54) via the buffer (50), and is input to the negative input of the operational amplifier (54).
Gl input to the gate of 5゜56.57.58),
The output differentially amplified with the gain determined by the G2 signal (see Figure 11) is output from the operational amplifier (54) to V os'
(See Figure 12).

Next, the determination of the integral level will be explained.

If the integration is forcibly terminated when the brightness is low, the level of the pixel output of the image sensor (13) will naturally be lower than when it is appropriate. Therefore, in this case, the above-mentioned brightness determination circuit (24) is used to detect the level of integration, and a gain is applied to the output of the image sensor (13) according to the result, so that an output at an appropriate level is always obtained. I'm trying to be able to do that.

The following will explain the brightness determination analog circuit of FIG. 8, the pulse timing chart of FIG. 9, the brightness determination logic circuit of FIG. 10, and the truth table of FIG. 24. Note that the brightness determination circuit (23) is constituted by this brightness determination analog circuit and the brightness determination logic circuit. As shown in FIG. 8, the operational amplifier (43) outputs an output V43-Vref- (DOS-AGCOS) corresponding to the amount of light that is darkened, and one comparator (45
) has been entered into minus human power. When determining the integration time, φd is applied as shown in FIG.
Vth) is input. Now, when the SH pulse occurs, latch 1 (73) and latch 2 (74) in Figure 1O are activated.
), latch 3 (75) are all reset.

After that, as shown in FIG. 9, when the φC pulse is generated, the FET (48) in FIG. 8 is turned on, and the positive input of the comparator (45) is
2) is input. Here, if DOS-AGCOS)>Vth/2, the output VFLG of the comparator (45) is “I
]”, and the AND gate (
70) becomes "H", and latch 1 (73) is set. After that, as shown in FIG. 9, when the φb pulse is generated, the FET (47) in FIG. 8 is turned on.
The positive input of the comparator (45) has (V ref
-V th/4) is manually applied. Here, if D
OS-AGCOS)>VLh/4, the output of the comparator (45) V F L G
becomes "11", and in Figure 1O, the AND gate (
71) becomes "H", and latch 2 (74) is set. Furthermore, after that, as shown in FIG.
When a pulse is generated, F"ET (46) in Fig. 8 is turned on, and the positive power of the comparator (45) is (V).
rer −V th/ 8 ) is input. here,
(DOS-AGCOS)>Vth/8, the output VFLG of the comparator (45) is “1”.
1", the output of the AND gate (72) shown in FIG. 1O becomes "H", and latch 3 (75) is set.

For each of the above cases, G1 is determined according to the truth table in Figure 24.
．． G3 signal is generated. Based on this signal, the gains are selected as shown in the table below, each with approximately the appropriate level of Vos.
is obtained.

In this way, by sequentially turning on the FETs (49, 48, 47, 46), the base QN pressure generation circuit (RVC
) generates a plurality of reference voltages, one comparator (45) can determine brightness in multiple stages, and the number of comparators formed on the same chip as the image sensor (13) can be reduced.

The FET (44) shown in Figure 8 is in INT mode and DD mode.
! This is a switch for supplying power to the resistance divider circuit, that is, the reference voltage generation circuit (RVC) only in the mode.

This FET (44) allows the base Q voltage generation circuit (RV
C) is energized only when brightness determination is necessary, reducing current consumption. This saving effect on current consumption becomes greater at high brightness because the integration time becomes shorter than the readout time.

As shown in FIG. 11, the signal V os'
), a capacitor (62), and a buffer (64).
It is input to the minus input of (65). This signal Vos
' is held by the signal processing timing generator (21
) to φ,=“YES”, and is performed by an OSS/H pulse signal generated at the timing of signal charge transfer of φ2−“H”. The signal Vos' is also input to a sample and hold circuit consisting of an FET (59), a capacitor (61), and a buffer (63). This sample bold circuit samples and holds the output of the black reference pixel subjected to AC light shielding as shown in FIG. The pulse that provides sample and hold timing is the OBS/H signal shown in FIG. 12, which is generated in the sequence shown below.

As shown in FIGS. 2 and 12, after shifting from the INT mode to the DD+ mode, an ADS signal that provides timing for starting A/D conversion appears in the ADT signal. The microcomputer (14) measures the timing of sample and hold of the black-based pixel output while monitoring this signal. The microcomputer (14) outputs NB while outputting the black reference pixel.

-"11" and NB2-"H", and the signal processing timing generating section (21) thereby sets the OBS/I-1 signal to "H". Continued development of microcomputers (
14) is NB until the next ADS signal rises.

-“L”, NB, -“H” are output, and the signal processing timing generation unit (2I) outputs the OBS/H signal as “L”.
”.As a result of the above, the FET (59) shown in FIG.
, a capacitor (61), and a buffer (63) holds the input black reference pixel output and inputs it to the negative input of operational amplifier 2 (65). After the sample bolding of the black-based pixel, the output of operational amplifier 2 (65) is subtracted by the amount corresponding to the bolded black-based pixel output, and the output of the operational amplifier 2 (65) is subtracted by the amount corresponding to the bolded black-based pixel output, and the G3. It is amplified by the gain determined by the G4 signal (distinction table 11) and output as a signal Vos (FIG. 12).

As described above, the output signal O8 of the image sensor (13) is double sampled in the AGC differential amplifier circuit (25) and the OB subtraction AGC differential amplifier circuit (26), the reset level is subtracted from the signal level, and the reset level is subtracted from the signal level. A signal without the influence of noise is extracted, and the black reference level is further subtracted from the signal without the influence of reset noise, resulting in an output Vos in which the dark output is removed from the output of each pixel.
is obtained. Furthermore, this output Vos is applied to the AGC differential amplifier circuit (
25) and the OB subtraction AGC differential amplifier circuit (26), a gain of x8 to x64 is applied, as described later, according to the average level of each pixel output. In this way, since the two amplifier circuits (25, 26) perform two-stage amplification, the range of resistance values connected to the operational amplifier (54, 64) can be smaller than when amplifying with one amplifier circuit. , the area occupied by the resistor becomes smaller.

Next, the gain of the operational amplifier (54) of the AGC differential amplifier circuit (25) and the gain of the operational amplifier (65) of the OB subtraction AGC differential amplifier circuit (26) shown in FIG. 11 will be described. Here, for the output OS of the image sensor (13), x8. XI6. In order to switch the gain of
(65) performs two-stage gain switching. In this case, the operational amplifiers (54) and (65) always have an offset problem. When applying gain in two stages, the first stage gain is GNI, the second stage gain is GN2,
If the offset of each operational amplifier is Δv1, the manual power is Vi1, and the output is ■0, then the output is expressed by the following formula.

Vo-((Vi+△V)XGNI+△V) X GN2
-ViXGNIXGN2+△V・(GNlxGN2+G
N2) = (Vi 1△V) X GNI X GN2
+ΔV x GN If the total gain GNIXGN2 of the 22-stage operational amplifier does not change, an offset due to GN2 appears in the second term (ΔVX GN 2 ) of the above equation.

That is, the smaller GN2 is, the smaller the total offset will be.

Therefore, the first stage gain GNI is the second stage gain CN2.
Although the offset can be suppressed by choosing a value higher than , the offset remains even with this measure. For this reason,
As shown in FIG. 11, the operational amplifier 2 (65) in the latter stage always performs A/D conversion because it performs a level shift using a voltage that is one minute potential drop from the reference voltage V rer through the diode (99, which is the bias means) as a standard. The offset is made to appear on the lower voltage side than the reference voltage V rer as much as possible.

After sampling and holding the signal representing the black reference pixel, the OB subtraction AGC differential amplifier circuit (26) outputs a signal representing the second black reference pixel subjected to Ai2 light shielding before outputting the signal representing the effective pixel. are doing. Since the previously bolded black reference pixel is subtracted from the output representing the second black reference pixel, an output matching the reference voltage Vref is obtained if there is no offset of the operational amplifier. However, since the output of the operational amplifier 2 (65) always has an offset Voffset on the lower voltage side than the reference voltage V ref, the output becomes (Vref - Voffset). A/D this
Upon conversion, a signal corresponding to VolTset is obtained as digital data. From now on, the output of effective pixels is this V
The offset amount is subtracted by the calculation of the microcomputer (14), so the microcomputer (I4)
) is essentially the same data with the offset component removed.

Next, the DD2 mode will be explained.

In the DD2 mode, the image sensor (13) is not caused to perform any active operation.

Therefore, the NB connected to the I10 buffer (22),
, switches the human output of the NB2 signal, outputs the G1 signal to NB, the G3 signal to NB, and the microcomputer (
14), the gain information of the output of the image sensor (13) is notified. This I10 switching is performed by the DD2 signal.

Only in the DD2 mode, the signal output as Vout is the output Vos of the image sensor (13).

The pixels used in this system are image sensors (13)
are pixels detected in two separate regions of
No photodiode (PD) is provided between the two regions. When outputting the output of these pixels as Vout to the A/D converter (15), there are problems that will be described later, so by switching between DD2 mode and DD1 mode,
Vos is output as Vout only when valid pixels are output. The output Vos' of the AGC differential amplifier circuit (25) is the output component Vo corresponding to the optical signal when the effective pixel is output.
s' (sig) and the dark output component V os' (dark
) expressed as the sum of (V os' = V os'
(sig) + Vos' (dark)). O
V os' (
dark) is subtracted, and Vos= V ref −G N 2
-Vos' (dark)) as the A/D converter (1
5) is output.

At this time, the output of the pixel from which the photodiode (PD) has been removed becomes Vos'-0 because there is no output corresponding to the optical signal and no dark output component. Here, when Vos' (dark) is subtracted by the OB subtraction AGC differential amplification (26), Vos = Vref - GN2 x (0 - Vos' (dark).
k))>Vref, and the reference voltage V that can be A/D converted
re “Contrary to the lower voltage side, Vos is the reference voltage V r
The voltage becomes higher than er, which exceeds the dynamic range of A/D conversion, and may lead to destruction of the A/D conversion section (15). For this reason, other than the output of effective pixels,
Analog switches (28) and (29) are switched to constantly output an A/D convertible temperature detection output VTMP. In this way, only when outputting effective pixels, DD2-
By outputting Vos as “H” and outputting VTMP as DD2-“L” when an invalid pixel is output, the A/D conversion is always within the dynamic range of A/D conversion.
I am trying to do the conversion.

This concludes the explanation of the DD2 mode and the explanation of the first embodiment.

Next, a second embodiment will be described in which the means for removing the dark output component in the first embodiment is modified. here,
Only the differences from the first embodiment will be explained with reference to the block diagram in FIG. 14 and the circuit diagram of the AGC differential amplifier circuit in FIG. 15.

First, the block diagram of FIG. 14 showing the second embodiment and the block diagram of FIG.
As shown by the differences in the block diagram of FIG. 2 illustrating an embodiment of the analog reference voltage V re
This embodiment differs from the first embodiment in that r' is output from the AGC differential amplifier circuit (+25). Further, in FIG. 14, the O B SR calculation AGC differential amplifier circuit in the first embodiment is removed.

The operation of the second embodiment will be explained with reference to FIG. As in the first embodiment, the image sensor (13) outputs the output of the black reference pixel before outputting the effective pixel. Here, A
A sample bold circuit consisting of an FET (159), a capacitor (161) and a buffer (163) in the GC differential amplifier circuit (125) samples and holds the output of the black reference pixel using the OBS/H pulse. In the first embodiment, the held output was connected to the negative power of operational amplifier 2 (65) and subtraction was performed by operational amplifier 2 (65), but in the second embodiment, the held output was connected to the negative power of operational amplifier 2 (65), but in the second embodiment, the held output ' is output as '. This V rer' is A
The voltage is connected to the /D converter (+15) as an analog reference voltage, and the A/D converter (115) A/D converts the input voltage using this voltage as a reference.

That is, in order to take the difference between the human power Vout and the reference voltage V red and convert it into a digital value, an A/D converter (
This is equivalent to subtracting the black reference pixel output in 115).

In addition, the output of the black reference pixel, which is sampled and held by the sample and hold circuit consisting of FET (+60), capacitor (+62), and buffer (164), and the output of each effective pixel are the outputs of operational amplifier 2 (165). , these differentials are taken within the A/D converter (115), so the offset of operational amplifier 2 (165) is completely removed. Therefore, in the second embodiment, the dark output of the image sensor (13) is removed and the operational amplifier 2 (
165) offset removal is performed.

Next, a third embodiment will be described with reference to FIGS. 16, 17, and 18. In this third embodiment, the dark output removal means is the first! , is different from the second embodiment.

First, let us look at the block diagram of the third embodiment (Fig. 16) and the block diagram of the first embodiment.
Differences from the block diagram of the embodiment (FIG. 2) will be described.

In the third embodiment, the sample and hold pulse OBS/H of the black reference pixel is input to the A/D converter (215), and the OB subtraction AGC differential amplifier circuit is removed. In this third embodiment, subtraction of the black reference pixel is performed within the A/D converter (215).

FIG. 18 shows the A/D converter (215), and this A/D converter (215)
The conversion section (215) includes an A/D conversion circuit (206) and an internal circuit provided on the same chip. The output of the image sensor inputted as Vin in FIG. 18 consists of the output of the black reference pixel and the subsequent effective pixels. The output of the black reference pixel is output from FET (201) by OBS/H pulse.
Sample and hold is performed by a sample and hold circuit consisting of a capacitor (202) and a buffer (203). The effective pixel output that is input from then on is the operational amplifier (
205), the sample bolded black reference pixel output is subtracted therefrom, and then input to the A/D conversion circuit (206).

FIG. 17 shows an AGC differential amplifier circuit (225).

In the first embodiment, there was a sample bold circuit for the output of the black reference pixel, but in the third embodiment, this is removed. Further, as in the second embodiment, since the black reference pixel output and the effective pixel output are output from the same operational amplifier (165), the offset of this operational amplifier (165) is completely canceled.

Next, a fourth example in which the dark time output removing means is different from the above-mentioned embodiment.
An example will be explained. FIG. 19 is a hardware block diagram according to the fourth embodiment. This is different from FIG. 16, which is a block diagram of the third embodiment, when the reference voltage V re
The difference is that r is not input manually to the A/D converter (315), and the AGC differential amplifier circuit (225) has exactly the same configuration as the third embodiment.

FIG. 20 shows the A/D converter (315), and this A/D converter (315)
The conversion section (315) includes an A/D conversion circuit (405) and an internal circuit provided on the same chip. While the image sensor (13) is outputting the black reference pixel,
The OBS/H pulse is given to the /D converter (315), and the output of the black reference pixel input to the terminal Vin becomes FE.
T (401), capacitor (402), buffer (40
3) is sampled and held by the sample and hold circuit consisting of the following. The held black reference pixel output is input to the A/D conversion circuit (405) as an analog reference voltage (V rer' ). From then on, the effective pixel output of the image sensor (I3) input to the terminal Vin is the second
Similar to the example, the bolded black reference pixel output (V
rel") is subtracted and then A/D converted. As a result, the dark output component is removed.

<Effects of the Invention> As is clear from the above, the solid-state imaging device of the present invention has the following effects:
a plurality of photoelectric conversion units, at least one of which is shielded from light and corresponding to at least the used pixel and the black reference pixel; a subtraction means for subtracting the output corresponding to the black reference pixel from the output corresponding to the used pixel; and a subtraction unit that is limited within a certain range. a fixed range voltage output means for outputting the voltage determined by the pixel, a storage section for accumulating the charge from each photoelectric conversion section, and the subtraction means output a subtracted value of the output corresponding to the black reference pixel from the output corresponding to the pixel in use. If the output is in the A/D converter, the output is manually input to the A/D converter, and in other cases, the output of the fixed range voltage output means is manually input to the A/D converter. The converter can always input signals within the human input range, and the A/
There is no risk of destroying the D conversion section due to overcurrent.

In addition, in the case where the fixed range voltage output means is a resistor divider circuit and a switch is provided between the resistor divider circuit and the power supply,
When the output of the resistor divider circuit is not input to the A/D converter, the switch can be turned off to save power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the image sensor in the solid-state imaging device of the present invention, FIG. 2 is a block diagram of the fixed imaging device of the first embodiment of the invention, and FIG. 3 shows the potential structure of the image sensor at the time of initialization. 4 is a time chart of the signal in the initialization mode of the first embodiment, FIG. 5 is a diagram showing the potential structure of the image sensor in the integral mode, and FIG. 6 is a time chart of the signal in the integral mode. Fig. 7 is a structural diagram of a compensation diode, Fig. 8 is a circuit diagram of a luminance judgment analog circuit, Fig. 9 is a time chart of signals during luminance judgment,
FIG. 10 is a circuit diagram of the brightness determination logic circuit, FIG. 11 is a circuit diagram of the AGC differential amplifier circuit and the OB subtraction AGC differential amplifier circuit in the first embodiment, FIG. 12 is a time chart regarding pixel output processing, and FIG. The figure is a circuit diagram of the temperature detection section, Figure 14 is a block diagram of the solid-state imaging device of the second embodiment, Figure 15 is a circuit diagram of the AGC operational amplifier circuit of the second embodiment, and Figure 16 is the third embodiment. 17 is a circuit diagram of the AGC operational amplifier circuit of the third embodiment, FIG. 18 is a circuit diagram of the A/D conversion section, and FIG. 19 is a block diagram of the solid-state imaging device of the fourth embodiment. 20 is a circuit diagram of the A/D conversion section of the fourth embodiment, FIG. 21 is a structural diagram of the image sensor, and FIG. 22 is a time chart of signals in the integration mode of the fourth embodiment. FIG. 23 is a diagram explaining the transfer of dark charges, and FIG. 24 is a diagram showing a truth table of the brightness determination logic circuit. PD, BG, ST...Storage means, SH...Shift gate, RG...Transfer register,
RG I CG... Integral clear gate, 14... Microcomputer, 20... Integral time control section, 23. Mode selection circuit, 2
4... Brightness determination circuit, 30... Transfer lock generation unit. Patent applicant: Minolta Camera Co., Ltd. Agent: Patent attorney: Mr. Aoki and two others Figure 3 (a) (G) Peripheral table Lb 7 Figure circumference izt length La La wealth 7.71J

Claims (4)

[Claims] (1) A plurality of photoelectric conversion units, at least one of which is shielded from light, and which corresponds to at least the pixel used in the system and the black reference pixel; an accumulation unit that accumulates charges from each of the photoelectric conversion units; subtraction means for at least subtracting the output of the storage section corresponding to the black reference pixel from the output of the corresponding storage section; fixed range voltage output means for outputting a voltage limited to a certain range; When outputting a subtracted value of the output of the storage section corresponding to the black reference pixel from the output of the storage section corresponding to the pixel, this subtraction value is input to the A/D conversion section, while the subtraction means , when the subtracted value of the output of the storage section corresponding to the black reference pixel from the output of the storage section corresponding to the pixel in use is not output, the output of the fixed range voltage output means is sent to the A/D conversion section. A solid-state imaging device comprising an input switch. (2) The solid-state imaging device according to claim 1, wherein the fixed range voltage output means is a resistance divider circuit that divides the reference voltage by a resistor string. (3) The solid-state imaging device according to claim 2, wherein the resistor divider circuit includes a switch provided between a resistor string and a power source. (4) In the solid-state imaging device according to claim 3, the subtraction means outputs a subtracted value of the output of the storage section corresponding to the black reference pixel from the output of the storage section corresponding to the pixel used. If the solid-state imaging device is a solid-state imaging device, the switch is turned off by the mode selection circuit.