JPH01208043A - Change-over switch circuit for duplicate system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a duplex system changeover switch circuit that has a function to prevent high-frequency oscillation that occurs when alarm signals from both systems input to the duplex system changeover switch are restored at the same time, and which oscillates in any case. The purpose of this system is to provide a redundant system changeover switch circuit that operates normally without any damage to the system. and a delay time setting means for setting a predetermined delay difference between switching operations of the first and second switching means. constitutes.

[Industrial application field]

The present invention relates to a duplex system changeover switch circuit having a function of preventing high frequency oscillation that occurs when alarm signals of both systems input to a duplex system changeover switch are restored at the same time.

For example, in a circuit or transmission line system that distributes data to multiple routes, such as in a synchronous terminal device, a redundant system is used to switch the system to the other route if one route goes down. A switching switch method is adopted.

One of the simplest circuit configurations of such redundant system switching switch circuits and one that is widely used is one that uses a NAND gate circuit and a delay circuit.

This redundant system changeover switch circuit may cause a high frequency oscillation effect when the alarm signals of both systems are restored at the same time, and it is necessary to take measures against such an effect.

[Conventional technology]

FIG. 4 is a diagram for explaining a conventional example, and FIG. 5 is a diagram for explaining a time chart during oscillation in the conventional example.

The redundant system changeover switch circuit 100 shown in FIG. 4 consists of a changeover switch 1 corresponding to the 0 system and a changeover switch 2 corresponding to the 1st system. ) 11.21 and a predetermined delay time 1d□.

A delay circuit 12.22 having td4 is provided.

Furthermore, the delay time DLO is determined by the delay time td2 of the delay circuit 12 and the output of the 0-system NAND circuit 11 of the 1-system NAND.
This includes a delay up to the input of the D circuit 21.

Furthermore, the delay time DL1 is determined by the delay time td4 of the delay circuit 22 and the NA of the 0 system when the output of the NAND circuit 21 of the 1 system
This includes a delay up to the input of the ND circuit 11.

Note that the delay time tdl+td3 means a delay time inherent to the NAND circuit 11.21.

Alarm signal input to selector switch 1.2 *ALM
O■, *ALM1■ are inverted signals of the alarm signal ALM0.1, and when it is "low", it means that an alarm has occurred.

Further, the output (bl, (d)) of the NAND circuit 11.21 is "low" and acts to activate the corresponding control circuit 3.4 and activate the transmission path.

Such a duplex system changeover switch circuit 100 is configured to duplex in order to improve the reliability of an important device such as a synchronous terminal device that performs an operation such as distributing a large amount of data to each route. When a system goes down, it switches to another system and takes political action.

That is, for example, if the O system, which is the current active system, becomes impaired and data transmission becomes impossible, a monitoring circuit (not shown) detects this and sends out an alarm signal.

Alarm signal *AL which is the inverted signal of this alarm signal
The NAND circuit 11 in the selector switch 1 receives MO■,
The "low" output (a) of the delay circuit 22 outputs NANDL, and its output (b) outputs "high", which is sent to the delay circuit 1.
2 to the NAND circuit 21 of the 1st system.

Alarm signal *AL input to the NAND circuit 21 of system 1
Since M1■ is in the recovery state and is in the “high” state, N
The signal via the AND circuit 21 (dl becomes “low”,
The control circuit 4 of the 1st system becomes active.

In the duplex system changeover switch circuit described above, for example, if both the O system and 1 system are alarmed, and the alarms are restored at the same time, the alarm signals *ALMO■ and *ALM1■ will be as follows.
As shown in Figure 5, the N
The input sides of the AND circuits 11 and 21 are both in the "high" state.

Then, the output (b) of the NAND circuit 11 changes from "high" to "low" after the delay time tdl of the NAND circuit 11, and at the same time, the output (d) of the NAND circuit 21 also changes from "high" to "low".
After the delay time td3 of the circuit 21, it changes from "high" to "low".

, Next, when the output (bl, (d) becomes "low", the output (C1, (al) of the delay circuit 12.22 also reaches the delay time tdg
+L Changes from "high" to "low" after 44 seconds.

When the output (C1, (a) changes from "high" to "low", the outputs (b), (d) of the NAND circuit 11 change from "low" to "high" after a delay time tdlrtai, and similarly the output (C1, (a) changes from "low" to "high"). C1, (a) also has a delay time 'd2+ t-
After d4, the operation of changing from "low" to "high" is repeated.

[Problems to be Solved by the Invention] As shown in FIG. 4, the redundant system changeover switch circuit 100 that switches the system after a predetermined delay time has a delay time of l/delay between the changeover switches 1 and 2 as described above. It will oscillate with a period of tdl.

That is, if the delay time t, 1=several n5ec, then O system.

If the alarms are restored at the same time on both systems, oscillation will occur at several tens of MHz.

An object of the present invention is to provide a duplex system changeover switch circuit that operates normally without oscillating under any circumstances.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

10°20 in the principle block diagram of the present invention shown in Fig. 1 corresponds to the response when the act system of the circuit or line, which is composed of a dual system of 0 system and 1 system, becomes a failure and alarm signals ■ and ■ are generated. First and second switching means 10 and 20 generate switching signals 1 and 2 with a predetermined delay time for switching to the system. It is a delay time setting means for setting the delay time, and when the alarm signals ■ and ■ are generated in both systems and are restored at the same time, the switching operation of the first and second switching means 10゜20 is stabilized in either system. By configuring it so that

[For production]

The delay time setting means 30 determines the difference between the delay time systems for switching the first and second switching means 10.20 to the corresponding second and first switching means 20.10 with a predetermined delay time. Set it up and set it up.

For example, the first and second alarm signals ■.

When ■ is restored at the same time, the first and second switching means 10
．． Due to the difference in delay time between the switching operations of 20, by making one of them act, a stable state can be achieved and self-oscillation can be prevented.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a diagram for explaining details of the present invention, and FIG. 3 is a diagram for explaining a time chart in an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG.
The second switching means 10.20 includes a NAND circuit 11.21 similar to that explained in FIG. 4, a selector circuit 13.23, resistors R11, 21, and a capacitor C1l.
, 21, changeover switches 10a, 20a.

As the delay time setting means 30, the changeover switches 10a, 2
0a internal selector circuit 13.Resistor R11 for 23,
21 and capacitor C1l, select the signal ■, [phase] via 21, or select the output ■, ■ of the NAND circuit 11.21
This is an example of a redundant system changeover switch circuit 100a configured from a backboard 30a for setting ground (GND) and +5V for specifying whether to select.

The setting of the ground (GND) and +5■ for the selector circuit 13.23 is as shown in FIG.
Different settings are made so that the value is +5■.

Furthermore, when the selector circuit 13 or 23 is set to ground (GND), the signal ■ or the signal [phase] is selected and +5V
When set to , signal ■ or signal ■ is selected.

In this state, the selector switch 10a is in the active state, the signal (b) is at the "low" level, and the signal (dl) is at the "high" level.

At this time, if data transmission becomes impossible due to a failure in the transmission path of the 0 system, an alarm signal *A is sent from a monitoring panel (not shown), for example.
LMO■ (a "low" level signal) is generated and sent to one input terminal of the NAND circuit 11.

As a result, the output signal (b) of the NAND circuit 11 shifts from the "low" level to the "high" level.

The selector circuit 23 receives this “high” level output signal (b
) and select one input state g (C
1) Change from "low" level to "high" level.

The output signal (dl) of the NAND circuit 21 thereby shifts from the "high" level to the "low" level, and the 1 system is switched to the act system.

Note that the output signal (dl is the resistor R11 and capacitor C1
After a delay of a time constant of l, it is selected by the selector circuit 13 and becomes the input state of the NAND circuit 11 (al).

In addition, when the changeover switch 10a is in the active state, both the 0-system and 1-system transmission paths temporarily become impaired, causing an alarm signal *ALMO■.

* A L M 1■ both shift to “low” level,
Moreover, FIG. 3 shows the processing situation when the systems are restored at the same time.

When the alarm (No.K*ALMO■ becomes a "high" level), the output signal (b) of the NAND circuit 11 shifts from a "high" level to a "low" level after a delay time unique to the NAND circuit 11. .

Also, this output signal (b) is selected by the selector circuit 23 and becomes the signal (C1), so the signal (C1 is the NAND circuit 11
The output signal (b) changes to the "low" level and immediately becomes the "low" level.

Therefore, the output signal (d) of the NAND circuit 21 is such that when the alarm signal *ALM1 becomes the "high" level, the signal (C1 remains at the "high" level due to the difference in delay time). Therefore, when the signal (C1) shifts to the "low" level, it becomes "high" again.
level, and is stabilized in this state (that is, the state where the 0 system is the act system).

As described above, the 0-system changeover switch 10a and the 1-system changeover switch 20a have the same configuration, and by setting the delay time from the outside, high-frequency oscillation that may occur when two system alarms are restored at the same time can be prevented. This makes it possible to reliably prevent this.

〔Effect of the invention〕

According to the present invention as described above, it is possible to provide a duplex system changeover switch circuit that reliably prevents high frequency oscillations that occur when duplex system alarms are restored at the same time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart in an embodiment of the present invention, and FIG. 4 is a conventional example. FIG. 5 is a diagram illustrating a time chart during oscillation in the conventional example. In the figure, 1.10a and 2.20a are changeover switches, 3.4 is a control circuit, 10 is a first switching means, and IL21 is a NAND
12.22 is a delay circuit, 13.23 is a selector circuit, 20 is a second switching means, 30 is a delay time setting means, 30a is a backboard, and 100 and 100a are redundant system changeover switch circuits, respectively. FIG. 1 is a block diagram explaining the present invention in detail. FIG. 3 is a diagram explaining a time chart in an embodiment of the present invention.

Claims (1)

[Claims] When the act system of a circuit or line consisting of a dual system of 0 system and 1 system becomes faulty and an alarm signal ([1], [2]) is generated, a system for switching to the corresponding system is provided. Switching signal ([3],
[4]) are generated with a predetermined delay time.
switching means (10, 20); and delay time setting means (30) for setting a predetermined delay time difference between the switching operations of the first and second switching means (10, 20).
) A redundant system changeover switch circuit.