JPH01209876A - Interframe coding system - Google Patents

Abstract

PURPOSE:To improve coding efficiency by transmitting only picture element identification information in an effective block and suppressing the value of a decoding predictive error signal on an insignificant picture element. CONSTITUTION:A digital picture signal has an interframe difference 3 taken via a scanning converting circuit 2 to input significant/insignificant picture element identification information in the block decided to be the effective block in a significant/insignificant block and significant/insignificant picture element identification circuit 5 to a block identifying/picture element identification information coding circuit 6. The data of the circuit 6 is outputted to a multiplexing circuit 7 and a block identifying/picture element identification decoding circuit 11. An effective block coding circuit 8 encodes the output of the circuit 5 and outputs it to the circuit 7, decodes it at every block in an effective block decoding circuit 9, receives a quantizing noise generated consequently from the circuit 11 and suppresses the decoding predictive error signal of the insignificant picture element in a circuit 10, thereby, it is outputted to a frame memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to an interframe coding method for video signals.

(Prior Art) An interframe coding method is a method for highly efficient coding of signals with small subject movements, such as video conference video signals. Among them, one of the most efficient methods is to calculate the difference between the input image and the prediction signal constructed using the previous signal, that is, the prediction error signal, by a predetermined size consisting of multiple pixels. There is a method in which pixels are divided into blocks, and all pixels included in the block are subjected to processing such as back-to-back 1-hell quantization or orthogonal transform coding.

In these conventional methods, all pixels in a block are processed at once, so in blocks that include pixels with large prediction errors, the decoding prediction error of pixels with zero prediction errors is zero due to the influence of such pixels. It disappears. As a result, when the human subject moves, the decoding and prediction error of the surrounding pixels in the block containing the outline has some value even though it should be zero, and this value varies from frame to frame. To keep,
The drawback was that the image quality deteriorated, making it appear as if mosquitoes were flying around the subject. Due to these drawbacks, it is possible to reduce the amount of information by roughening the quantization characteristics of the signal by taking advantage of the visual characteristic that the brightness level discrimination sensitivity is generally low in the contour area, that is, the edge area. Despite this, it is necessary to quantize with high precision,
This has the disadvantage that encoding efficiency decreases.

Another conventional method that improves the conventional method is, for example, Japanese Patent Application No. 60-079875 entitled ``Coding Processing Method.'' In this method, in order to improve the image quality around the subject, in addition to the prediction error signal from the block processing described above, an existence/non-significance pixel identification signal is transmitted for pixels on the entire screen, and this signal is used to identify the non-significance pixels. Even if the decoded prediction error signal was not zero, it was converted to zero. Therefore, redundant signals are transmitted for the entire screen, which has the disadvantage of reducing encoding efficiency.

(Object of the Invention) The present invention aims to solve the above-mentioned drawback of the conventional method that the encoding efficiency decreases, and to provide an interframe encoding method that efficiently reduces image quality deterioration that occurs around a subject. This is the purpose.

(Structure of the Invention) (Features of the Invention and Differences from the Prior Art) According to claim (1) of the present invention, only the presence/absence pixel identification signal in a valid block is encoded and transmitted, and the For pixels whose presence/insignificance pixel identification signal indicates an insignificant pixel, the value of the decoded prediction error signal obtained by block processing is suppressed, and the frame! The most important feature is decoding for one period. The difference is that in the prior art, the presence/absence pixel identification signal is encoded and transmitted for the entire screen.

In claim (2) of the present invention,
Without transmitting an irrelevant pixel identification signal, a block including an edge portion is detected using the value of the decoded predicted pixel signal obtained by block processing on the transmitting and receiving sides, and the decoded predicted error among the pixels included in the block is detected. For pixels whose signal is smaller than a predetermined value, the most important feature is to suppress the prediction error signal of the pixel and perform interframe decoding.

Such a method is not found in the prior art.

(Embodiment) FIG. 1 is a block diagram of a transmitting and receiving side device according to an embodiment of the present invention. In FIG. 1, (1) is the transmitting side.

(11) indicates the receiving side, and (Ill) indicates the transmission path. In the numerical symbols in the figure, 1 is a digital signal input terminal, 2 is a scan conversion circuit, 3 is a subtraction circuit, 4,109 is a frame memory, 5 is a valid/invalid block/valid/insignificant pixel identification circuit, 6 is a block identification/side 7 is a multiplexing circuit, 8 is a valid block encoding circuit, 9.105 is a valid block decoding circuit, 10 and 106 are invalid block and meaningless pixel processing circuits, 11 and 107 are block identification and Pixel identification information decoding circuit, 12 and 108 are adder circuits, 13 and 103 are buffer memories, 14 and 102 are digital interface circuits, 15 is an encoded data output terminal, 100 is a digital transmission path, and 101 is an encoded data input terminal , 104 is a separation circuit, 110 is a scanning inverse conversion circuit, and 111 is a digital signal output terminal.

Next, the operation on the transmitting side in the above configuration will be described. First, the digitized image signal input from the digital signal input terminal 1 is sent to the scan conversion circuit 2 as shown in FIG. 2 (1).
As shown in the figure, the m-line input image signal (1) is
) rearranges the signals into a format such as As a result, pixel signals within a block consisting of m lines x n pixels are configured as a continuous signal sequence.

From the output of the scan conversion circuit 2 (FIG. 2(2)), the output value of the accumulated image signal of the previous one frame period in the frame memory 4 is subtracted by the subtraction circuit 3. The result of this subtraction, ie, the interframe difference value, becomes zero in the still area of the input image.

The valid/invalid block/valid/invalid pixel identification circuit 5 performs both block-by-block and pixel-by-pixel processing. That is, regarding a block consisting of m lines x n pixels, when the power phase of the pixels in the block is smaller than a predetermined threshold, this block is determined to be an invalid block, and the other blocks are determined to be valid blocks, and the obtained block is determined to be an invalid block. Valid and invalid block identification information is sent to the block identification/pixel identification information encoding circuit 6.

Furthermore, when the prediction error signal for each pixel of a pixel in a block determined to be a valid block is smaller than a predetermined threshold value, this pixel is determined to be an meaningless pixel.

Other pixels are determined to be significant pixels, and the obtained significant/insignificant pixel identification information is sent to the block identification/pixel identification information encoding circuit 6.

The block identification/pixel identification information encoding circuit 6 is in the front.

The block identification information and pixel identification information processed by the recorded/invalid block and valid/insignificant pixel identification circuit 5 are run-length coded, for example. In this case, there is a method of individually encoding the surface identification information, or a method of inserting pixel identification information in place of the block identification information in valid blocks and performing run-length encoding on invalid block information and pixel identification information. It is easy to make an analogy. Furthermore, it is clear that variable length coding can be used instead of run-length coding. The encoded data here is sent to the multiplexing circuit 7 and the block identification/pixel identification information decoding circuit II.

Further, the valid block encoding circuit 8 encodes the prediction error signal in the valid block supplied from the valid/invalid block/valid/insignificant pixel identification circuit 5 for each block and sends it to the multiplexing circuit 7. For this encoding, for example, a vector quantization method, an orthogonal transform encoding method represented by a #-losing cosine transform method, etc. are used.

The effective block decoding circuit 9 is the effective block encoding circuit 8.
The encoded output is decoded to obtain a decoded prediction error signal. As a result of performing encoding and decoding processing for each block, quantization noise f is generated even in the still area of one image, so the quantization noise in this area is processed as an invalid block and a block in the meaningless pixel processing circuit IO. Identification/pixel identification information decoding circuit!
Suppress by the decoded output of (2). Specifically, first, for a block whose output from the block identification/pixel identification information encoding circuit 6 represents an invalid block, the decoded prediction error signal, which is the output from the valid block decoding circuit 9, is set to zero. Then, decoded prediction error signals are suppressed for meaningless pixels within the effective block.

The adder circuit 12 adds the output of the invalid block and meaningless pixel processing circuit 10 and the output of the frame memory 4, and the result of this addition is delayed in the frame memory 4 by one frame period.

The multiplexing circuit 7 time-division multiplexes the output data of the block identification/pixel identification information encoding circuit 6 and the output data of the effective block encoding circuit 8, and this multiplexed data is subjected to speed smoothing in the buffer memory January 3. After that, it is configured into a transmission frame in the digital interface circuit 14, and further converted into a code format on the transmission path, for example, an AMI code,
Digital transmission line 10 via encoded data output terminal 15
Sent to 0.

On the receiving side, a signal input from an encoded data input terminal 101 is converted into a format that can be decoded in a digital interface circuit 102, and further the transmission frame is decomposed. This output is separated into block identification/pixel identification information and effective block encoding information by a separation circuit 104 in a buffer memory 103. The circuit from the effective block decoding circuit 105 to the frame memory 109 (1
06, 107, 108) are the circuits (10, 11, 108) from the effective block decoding circuit 9 to the frame memory 4 on the transmitting side.
Perform the same operation as 12).

The scanning inverse conversion circuit ito performs the inverse conversion of the scanning conversion circuit 2, and sends out the decoded image signal in the digital signal format to the digital signal output terminal Ill.

Next, an embodiment of claim (2) will be described. In this case, the presence/invalid block and presence/insignificance pixel identification circuit 5 in FIG. - Pixel identification information decoding circuit 11
．． 107 is made to function as a block identification information decoding circuit. This valid/invalid block identification circuit 5
Only invalid block determination is performed; therefore, identification encoding and decoding processing of valid/ineffective pixel identification information is not performed.

The invalid block and meaningless pixel processing circuits 10 and 106 are
For invalid blocks, the decoded prediction error signal is set to zero.

Then, if the effective block includes a decoded prediction error signal larger than the first predetermined threshold and also includes pixels smaller than the second predetermined threshold, the effective block is in the edge portion. , and suppresses the decoded prediction error signal of the pixel smaller than the second predetermined threshold.

(Effect of the invention) As explained above, according to claim (1) of the present invention, 1
without transmitting the presence/non-significance pixel identification information of the entire screen.
Since only the pixel identification information within the valid block is transmitted, there is an advantage that encoding efficiency can be improved.

According to claim (2) of the present invention, the decoded prediction error signal is suppressed only for pixels with a small decoded prediction error signal around the edge portion without transmitting significant/insignificant pixel identification information. Therefore, the quantization characteristics of the edge portion can be made coarser, and the encoding efficiency can be improved. Another advantage is that the image quality around the edges of the subject can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a transmitting/receiving device according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a scan conversion format. 1... Digital signal input terminal, 2... Scan conversion circuit, 3... Subtraction circuit, 4,109... Frame memory, 5... Valid/invalid block, valid/invalid image 1m separate circuit, 6...Block identification/pixel identification information encoding circuit, 7
. . . multiplexing circuit, 8 . . . effective block encoding circuit. 9.105... Effective block decoding circuit, 10°10
6... Invalid block, meaningless pixel processing circuit, 11.10
7...Block identification/image JAta-specific information decoding circuit,
12,108...Addition circuit, 13,103...Buffer memory, 14,102...Digital interface circuit, 15...Encoded data output terminal, 100
... Digital transmission line, 101 ... Encoded data input terminal, 104 ... Separation circuit, 110 ... Scanning inverse conversion circuit, 111 ... Digital signal output terminal. Patent Applicant: Nippon Telegraph and Telephone Corporation (2) 2 makan earthquake exchange roads Fig. 2

Claims (2)

[Claims] (1) Construct a prediction signal using a signal one field or more before the input video signal, divide the resulting prediction error signal into blocks of a predetermined size, and make the prediction error signal within the block a predetermined size. When it is smaller than the threshold value, this block is defined as an invalid block, and when it is larger than the threshold value, this block is defined as a valid block. For this valid block, the entire block is processed at once and the prediction error signal is encoded and transmitted. In the interframe coding method, in addition to the prediction error signal obtained by processing the entire block at once for effective blocks, when the prediction error signal for each pixel is smaller than a predetermined value, it is considered an insignificant pixel, and when it is greater than a predetermined value, it is considered a significant pixel. Defined as a pixel, these presence/insignificant pixel identification signals are encoded and transmitted, and on the transmitting and receiving sides, for pixels for which the obtained presence/insignificant pixel identification signal represents a non-significant pixel, the decoded prediction obtained by block processing is performed. suppress the value of the error signal,
An interframe encoding method characterized by interframe decoding. (2) Construct a prediction signal using a signal one field or more before the input video signal, divide the resulting prediction error signal into blocks of a predetermined size, and make the prediction error signal within the block a predetermined size. When it is smaller than the threshold value, this block is defined as an invalid block, and when it is larger than the threshold value, this block is defined as a valid block. For this valid block, the entire block is processed at once and the prediction error signal is encoded and transmitted. In the interframe coding method, on the transmitting and receiving sides, a block including an edge portion is detected using the value of the decoded prediction error signal obtained by block processing, and among the pixels included in the block, the decoded prediction error signal is detected. An interframe encoding method characterized by suppressing a prediction error signal of a pixel smaller than a predetermined value and performing interframe decoding.