JPH01213074A - Synchronous clamp circuit - Google Patents

Abstract

PURPOSE:To generate the clamp pulse of optimum pulse width respectively for plural video signals of different transmission systems by providing a reference pulse generation circuit, a clamp pulse generation circuit and a pulse width comparison control circuit, etc. CONSTITUTION:The reference pulse generation circuit 1 generates a reference pulse to show the common divisor of the pulse widths of the clamp pulses respectively optimum for the plural video signals of the different transmission systems, and the reference pulse is integrated by the clamp pulse generation circuit 2, and the clamp pulse is outputted. Next, the clamp pulse from the circuit 2 and the pulse width of the synchronizing signal of an input video signal detected by a synchronism detection circuit 5 are compared by the pulse width comparison control circuit 3, and the circuit 2 is controlled so that the pulse width of the clamp pulse comes optimum. Then, the clamp pulse is generated at timing at which the synchronizing signal is detected by the circuit 5. Thus, the generation of the clamp pulse whose pulse width is made optimum automatically correspondingly to the pulse widths of the synchronizing signals of the video signals of various kinds of the transmission systems comes possible, and circuit constitution can be miniaturized, and economization is realized.

Description

[Detailed Description of the Invention] [Summary] Regarding a synchronous clamp circuit used in a transmission device, a monitor device, etc. that handles a plurality of video signals with different transmission methods, an optimum pulse width is determined for each of the plurality of video signals with different transmission methods. A synchronous clamp circuit that generates a clamp pulse corresponding to a synchronization signal specific to each video signal from a plurality of video signals with different transmission methods, and performs clamping using the clamp pulse. A reference pulse generation circuit generates a reference pulse indicating a common divisor of the pulse widths of clamp pulses that are optimal for the plurality of video signals of different transmission methods, and the reference pulses from the reference pulse generation circuit are integrated. A clamp pulse generating circuit that generates the clamp pulse by comparing the pulse width of the clamp pulse from the clamp pulse generating circuit with the pulse width of the synchronization signal of the input video signal, and determining that the pulse width of the clamp pulse is optimal. The present invention includes a pulse width comparison control circuit for controlling the clamp pulse generation circuit so as to achieve the following.

[Industrial application field]

The present invention relates to a synchronous clamp circuit used in a transmission device, a monitor device, etc. that handles a plurality of video signals of different transmission methods.

Video signal transmission methods include NTSC, PAL, and SEC.
In addition to standard methods such as the AM method, methods that enable higher quality such as the HLO-PAL method have been put into practical use, and video transmission equipment, video monitor equipment, etc. It is desired that it can be used for both. Therefore, a synchronous clamp circuit has been proposed that clamps the video signal by generating a clamp pulse corresponding to a synchronization signal specific to a plurality of video signals of different transmission methods. There is a demand for further economicalization of such synchronous clamp circuits.

[Conventional technology]

For example, as shown in FIG. 3, the synchronization clamp circuit includes a clamp pulse generation circuit 31, a synchronization detection circuit 32, and a clamp switch circuit 33. The synchronization detection circuit 32 detects a synchronization signal from an input video signal. At that timing, a clamp pulse is generated from the clamp pulse generation circuit 31 and applied to the clamp switch circuit 33, and a clamp output signal in which the synchronization signal of the input video signal is clamped to a constant potential is output from the clamp switch circuit 33. .

FIG. 4 is an explanatory diagram of a horizontal synchronizing signal and a clamp pulse. The horizontal synchronizing signal shown in fa) is detected by the synchronization detection circuit 32, and based on it, the clamp pulse generation circuit 3
Clamp pulses shown in 1 to (b) are generated. In the figure, tl is the period of the horizontal synchronizing signal, t2 is the bottom time of the horizontal synchronizing signal, and t3 is the falling 50% of the horizontal synchronizing signal.
100% time, t4 is the pulse width of the clamp pulse, t
5 is the time from the 50% fall of the horizontal synchronizing signal until the clamp pulse is generated.

Regarding the aforementioned two systems, the NTSC system and the HLO-PAL system, at time t1. t2. Approximate values of t3 are shown in Table 1.

Table 1 The HLO-PAL system was developed as a high-definition television transmission system for AM transmission or baseband transmission, and transmits two color signals in line alternation to eliminate the influence of differential phase. This is a method that makes it difficult to receive.

Pulse width t of clamp pulse applicable to the above two methods
4 is determined by the following equation.

t4<t21I,. +t 3111+, -t 3111
In the case of 11X Table 1, t4=420ns+20ns-
127.1ns = 312.9ns. Actually, a circuit margin is required, so if this circuit margin is set to 5Qns, for example, it becomes t4#263ns, and a clamp pulse with this pulse width is generated from the clamp pulse generation circuit 31, and the clamp switch circuit 33 outputs the NTSC signal. It is possible to clamp the video signals of the HLO-PAL and HLO-PAL systems.

[Problem to be solved by the invention]

As mentioned above, the synchronization signals of video signals of different transmission methods have different periods and pulse widths. For example, the pulse width of the horizontal synchronization signal in the above-mentioned NTSC method and HLO-PAL method The ratio will be approximately 10:1. If such synchronization signals with widely different pulse widths are clamped by the clamp pulse from the shared clamp pulse generation circuit 31, it will be difficult to properly ramp the synchronization signals with wide pulse widths.

Therefore, a method has been proposed in which a clamp pulse generation circuit is provided that generates a clamp pulse with an optimum pulse width for each transmission method, and the clamp pulse is selectively used based on the result of determining the transmission method.

However, in order to be applicable to all systems, it is necessary to provide a large number of clamp pulse generation circuits, which has the drawback of increasing the size and cost of the device. Furthermore, new transmission systems cannot be handled without adding a new clamp pulse generation circuit that generates clamp pulses with pulse widths that are optimal for the transmission system, so there is a drawback of poor flexibility.

The present invention provides for a plurality of video signals with different transmission methods.
The purpose is to generate clamp pulses each having an optimal pulse width.

[Means to solve the problem]

The synchronous clamp circuit of the present invention automatically generates a clamp pulse with a pulse width suitable for the transmission method, and will be explained with reference to FIG.

A reference pulse generation circuit 1 generates a reference pulse that indicates a common divisor of the pulse widths of clamp pulses that are optimal for a plurality of video signals of different transmission methods, and a clamp switch that integrates the reference pulses from this reference pulse generation circuit 1. circuit 4
A clamp pulse generation circuit 2 that generates a clamp pulse to be added to the input video signal compares the pulse width of the clamp pulse from this clamp pulse generation circuit 2 with the pulse width of the synchronization signal of the input video signal, and determines the pulse width of the clamp pulse. It is equipped with a pulse width comparison control circuit 3 that controls the clamp pulse generation circuit 2 to optimize the clamp pulse generation circuit 2, and a clamp pulse is generated at the timing when a synchronization signal is detected by the synchronization detection circuit 5.

[Effect]

The pulse width comparison control circuit 3 compares the pulse width of the synchronization signal detected by the synchronization detection circuit 5 with the pulse width of the clamp pulse from the clamp pulse generation circuit 2, and compares the pulse width of the clamp pulse from the clamp pulse generation circuit 2. The width is controlled to be multiple times that of the reference pulse from the reference pulse IE times i1, and when the pulse width of the synchronization signal is wide,
By performing the comparison control process multiple times, it is possible to generate a clamp pulse with a pulse width that is optimal for the pulse width of the synchronization signal.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a reference pulse generation circuit, 12 is a clamp pulse generation circuit, 1
3 is a pulse width comparison control circuit, 14 is a clamp switch circuit, 15 is a synchronization detection circuit, 21 is a counter, 22 is a pulse output circuit, 23.24 is a flip-flop, 25 is an arithmetic circuit, 26 is a start detection circuit, and 27 is a This is a stop detection circuit.

The reference pulse generation circuit 11 generates a reference pulse that indicates a common divisor of the pulse widths of the synchronization signals of a plurality of video signals of different transmission methods, that is, a reference pulse that has a period that is a common divisor of the pulse widths of the plurality of types of synchronization signals. Then, this reference pulse is applied to the clamp pulse generation circuit 12. The clamp pulse generation circuit 12 includes a counter 21 and a pulse output circuit 22, and the pulse width comparison control circuit 13 includes flip-flops 23 and 24 and an arithmetic circuit 25. The synchronization detection circuit 15 includes a start detection circuit 26 that detects the beginning of the synchronization signal, and a stop detection circuit 27 that detects the tail of the synchronization signal.

When the start detection circuit 26 of the synchronization detection circuit 15 detects the beginning of the synchronization signal of the input video signal, the detection signal is added to the counter 21 and the start terminal st of the pulse output circuit 22, causing the counter 21 to start counting. , and causes the pulse output circuit 22 to start outputting a clamp pulse. The counter 21 precents the output value n of the arithmetic circuit 25, counts and amplifies the reference pulse from the reference pulse generation circuit 11, and adds a stop signal to the stop terminal sp of the pulse output circuit 22 by counting the precent value n. Stops output of clamp pulse.

Therefore, from the pulse output circuit 22, the start terminal st
A clamp pulse having a pulse width corresponding to the preset value n is output from when the detection signal is applied to the stop terminal sp until the stop signal is applied to the stop terminal sp.

In this case, the start detection circuit 26 (81) shown in FIG.
After detecting the 50% level of the falling edge of the horizontal synchronizing signal shown in , the pulse output circuit 2 is delayed by a time corresponding to the time t5 until the rising edge of the clamp pulse shown in tb+.
2, the output of the clamp pulse is started.

In addition, in the pulse width comparison control circuit 13, the detection signal at the tail end of the synchronization signal by the start detection circuit 27 is applied to the clock terminal C of the flip-flop 23, 24, and a clamp pulse is applied to the data terminal of the flip-flop 23. The n+1 output signal from the counter 21 is applied to the data terminal of the flip-flop 24. That is, the count output after the output of the clamp pulse is stopped is added. Therefore, the flip-flop 23 detects when the pulse width of the clamp pulse is wider than the pulse width of the synchronizing signal, and the flip-flop 24 detects when the pulse width of the clamp pulse is narrower than the pulse width of the synchronizing signal. become. Note that if the cycle of the reference pulse is shortened and the rise time of a synchronization signal with a wide pulse width is long compared to the cycle, the output signal of n+] from the counter 21 is set as n+2, etc., and the output signal is set as n+2, etc., after the clamp pulse. can be prevented from being applied to the changing portion of the synchronization signal.

The calculation circuit 25 calculates the presen l-value n according to the Q terminal output signal of the flip-flop 23.24.If the period of the reference pulse is T, the pulse width of the clamp pulse is nT, and this pulse width nT When nT>W with respect to the pulse width W of the synchronizing signal, the Q terminals of the flip-flops 23 and 24 become "1", so the arithmetic circuit 25
decreases the precent value n. Conversely, when nT<W, the Q terminals of the flip-flops 23 and 24 become "0", so the arithmetic circuit 25 increases the precent value n. Also, when nT"=W, the Q terminals of the flip-flops 23 and 24 become "0". is “0”
'', the Q terminal of the flip-flop 24 becomes '1'', so the arithmetic circuit 25 continues to hold the preset value n.

Therefore, even when the pulse width is relatively wide, such as the synchronization signal in the NTSC system, and when the pulse width is relatively narrow, such as the synchronization signal in the HLO-PAL system, , it is possible to automatically generate a clamp pulse with the optimum pulse width for each transmission method and clamp the synchronous signal portion.

Further, the arithmetic circuit 25 in the pulse width comparison control circuit 13 is
Since it does not involve complex calculations, there is no need to implement it with a relatively large-scale circuit configuration such as a microprocessor.
It can be realized with a relatively small-scale circuit configuration such as a counter and a pulse generation circuit, or a read-only memory (ROM) sequence circuit. It is also possible to shorten the time for convergence to the optimum pulse width by making the steps of addition and subtraction of the precent value n in the arithmetic circuit 25 variable. Furthermore, in the case where the device is only compatible with a known transmission method, it is also possible to configure the device to output a preset value n that is the optimum pulse width by comparing the pulse width of the synchronization signal and the pulse width of the clamp pulse. In addition, if an error occurs in detecting the pulse width of the synchronizing signal due to noise, etc., a protection circuit is added to the arithmetic circuit 25, and when a difference in pulse width is detected consecutively for a preset number of times or more, the preset value n It is also possible to update the .

〔Effect of the invention〕

As explained above, the present invention generates a reference pulse from the reference pulse generation circuit 1 that indicates a common divisor of the pulse widths of clamp pulses that are optimal for a plurality of video signals of different transmission methods, and converts the reference pulse into a clamp pulse. Generation circuit 2
The pulse width of this clamp pulse is compared with the pulse width of the synchronization signal of the input video signal by the pulse width comparison control circuit 3, and the pulse width of the clamp pulse is optimized. , which controls the clamp pulse generation circuit 2.

Therefore, with the same circuit configuration, it is possible to automatically generate a clamp pulse with an optimal pulse width corresponding to the pulse width of the synchronization signal of the video signal of various transmission methods, which allows for miniaturization of the synchronization clamp circuit. This has the advantage of being economical.

Further, unknown transmission methods can be easily dealt with by reducing the period of the reference pulse. Furthermore, for known transmission systems, by programming the optimum pulse width, it is possible to switch to and output the clamp pulse with the optimum pulse width corresponding to the input video signal, thereby speeding up the convergence time.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a conventional example, and Fig. 4 is an explanatory diagram of a horizontal synchronizing signal and a clamp pulse. . 1 is a reference pulse generation circuit, 2 is a clamp pulse generation circuit, 3 is a pulse width comparison control circuit, 4 is a clamp switch circuit, 5 is a synchronization detection circuit, 11 is a reference pulse generation circuit, 1
2 is a clamp pulse generation circuit, 13 is a pulse width comparison control circuit, 14 is a clamp switch circuit, 15 is a synchronization detection circuit, 21 is a counter, 22 is a pulse output circuit, 23.2
4 is a flip-flop, 25 is an arithmetic circuit, 26 is a start detection circuit, and 27 is a stop detection circuit.

Claims (1)

[Scope of Claims] A synchronous clamp circuit that generates a clamp pulse corresponding to a synchronization signal specific to each video signal from a plurality of video signals of different transmission methods, and performs clamping using the clamp pulse, comprising: a reference pulse generation circuit (1) that generates a reference pulse that indicates a common divisor of the pulse widths of clamp pulses that are optimal for a plurality of video signals; Clamp pulse generation circuit (
2), and compares the pulse width of the clamp pulse from the clamp pulse generation circuit (2) with the pulse width of the synchronization signal of the input video signal, and adjusts the clamp pulse so that the pulse width of the clamp pulse is optimal. A synchronous clamp circuit comprising a pulse width comparison control circuit (3) that controls a pulse generation circuit (2).