JPH012146A - arithmetic processing unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an arithmetic processing device that recovers processing by retrying instructions in the event of a hardware failure.

(Prior Art) Conventionally, when a hardware failure is detected in a computer (mainly a central processing unit), a retry is attempted at the instruction level. However, at this time, the registers in the central processing unit (e.g. general register, index register,
If rewriting of the pace register or rewriting of the main memory is performed during the execution of an instruction that is subject to retry, retry at the instruction level is not possible because the integrity of the rewritten data is not guaranteed. The job that was being executed will be aborted.

FIG. 3 is a block diagram showing an example of the relationship between the register group and the arithmetic unit of the conventional arithmetic processing device.

The data output from the A and B output ports of register file 1, which includes a 2-output 1-person port type general register, index register, etc., is sent to multiplexers 2 and 3.
is selected and input to the arithmetic unit 4. The calculation result of the calculation unit 4 is shifted by the shifter 5 and then output to the input port of the register file 1. However, the register position of the input port of register file 1 is AMO290.
Similarly to the 14-pill to slice microprocessor, this is the same register location as indicated by the B port of the output port. If a failure detection circuit (not shown here) detects that a hardware failure occurred during the previous execution cycle in the next cycle after executing a write operation to register file 1, it stops the operation of the central processing unit. transfers control to a recovery routine and attempts to retry the instruction.

FIG. 4 is a processing flowchart of the arithmetic processing unit during the above-mentioned retry. When a failure is detected in step 401, it is determined in step 402 whether or not a write process was performed to the register and main memory during the retry target instruction, and if so, an abord process is performed and no write is performed. In this case, after executing the recovery processing routine on Stella 403,
Instructions are resumed at step 404.

In addition, in order to reliably detect hardware failures in the arithmetic processing unit, the arithmetic circuits used are duplicated, the results of each calculation are compared, and the data is written to the register after confirming that no failure has occurred. Some did. In this method, one operation is executed in two cycles of calculation + write, so it is often used in conjunction with the pipeline method, and if a failure occurs, registers are not rewritten, so the ) It is possible to reduce the possibility that the instruction (e) cannot be retried.

FIG. 5 is a block diagram showing an example of the relationship between the register group and the arithmetic unit of an arithmetic processing device in which the arithmetic operation and writing are performed in two cycles. Read data output from output ports A and B of the register file 50 is input to the arithmetic unit 56 via multiplexers 54 and 55, and is operated there. The result of this operation is shifted by the shifter 57 and then written to the work register 53 via the multiplexer 51.

When a verification circuit (not shown) confirms that no hardware failure has occurred in this cycle, the contents of the work register 53 are read into the register file 5ot4 in the next cycle. Note that, since the work register 52 temporarily holds the contents read from the output port A of the register file 50, the contents of the work registers 52 and 53 can be used again as calculation data of the arithmetic unit 56 as necessary. In this method, as mentioned above, the calculation result is 1
Since the data is not written into the register file 1 in cycles, even if a failure occurs, the register file will not be rewritten, increasing the possibility that the instruction can be retried. However, since this method requires two cycles for one basic operation, it is unsuitable for computers equipped with instructions that require complex control by firmware.

(Problems to be Solved by the Invention) In a conventional arithmetic processing device that rewrites registers and the like at the same time as an operation, if the rewriting occurs during the execution of an instruction that is to be retried when a hardware failure occurs, The drawback is that command retry is rarely possible. Therefore, in order to avoid this drawback, arithmetic processing units that perform one operation of calculation and writing in two cycles are not suitable for computers equipped with instructions that require complex control because one basic operation requires two cycles. It had the disadvantage of being. Therefore, the present invention aims to eliminate the above-mentioned drawbacks by performing calculation and writing in the same cycle, preserving information from one cycle before a hardware failure occurs, and making it possible to retry the instruction when the failure occurs. It is an object of the present invention to provide an arithmetic processing device that can immediately avoid temporary hardware failures.

[Structure of the Invention] (Means for Solving the Problems) The present invention has a register file consisting of a plurality of registers that read and write data as instructions are executed, and also allows instruction retry when a hardware failure is detected. In an arithmetic processing device that performs
a second register that holds register position information to which the information held in the register was written; a flip-flop that indicates whether data was written to the register file in the previous step; and a control means that performs processing to return the data in the register file to the state before the rewriting based on the contents of the first and second registers when it is determined that the file has been rewritten. .

(Function) In the arithmetic processing device of the present invention, when data is written to the register file with the execution of an instruction, the first register retains the information held in the register file before rewriting, and the second register retains the information held in the register file before being rewritten. The register holds register position information to which the information held in the first register was written, and the flip-flop indicates whether data was written to the register file in the previous step. When it is determined that the register file has been rewritten by the flip-flop, the control means performs a process of returning the data in the register file to the state before rewriting based on the contents of the first and second registers. Therefore, the preserved information in the register file can be used when retrying an instruction, and the possibility of retrying an instruction is significantly increased.

(Example) An example of the present invention will be described below with reference to the drawings, in which the same parts as those of the conventional example are denoted by the same reference numerals. FIG. 1 is a block diagram showing an embodiment of an arithmetic processing device of the present invention. 1 includes general register, index register, etc. 2
Assume that in the register file of the one-output port system, the register position of the input port is the register position indicated by the B port of the two output ports. 2 and 3 are multiplexers that select and output signals; 4 is multiplexer 2 and 3;
5 is a shifter that shifts the operation result and outputs it to register file 1. 6 is a shifter that register file 1 holds just before new data is written to register file 1. 7 is a register that holds the register position in the register file of the data written to register 6, and 8 is a flip-flop register that indicates that register file 1 was written in the previous step. P,
9 is a flip-flop indicating that the software instruction has been completed in the previous step.

Next, the operation of this embodiment will be explained. Data 110 and 111 read from the register file 1 are selected by multiplexers 2 and 3, respectively, and become input data 112 and 113 to the arithmetic unit 4. Arithmetic unit 4 is R+S-'Y
The calculation is performed and the resultant data month 4 is output to the shifter 5. The shifter 5 outputs the input data 114 as it is to the input port of the register file 1 without performing a shift operation. In register file 1, input data 114 is written to the register location indicated by the B output port. At the same time as this write operation, the read data 111 output from the B output port is written to the register 6, and the register position indicated by the B output port is written to the register 7.

Here, after the series of operations described above is completed, it is assumed that a detection circuit (not shown) detects that the calculation is not normal due to, for example, a temporary failure in the calculation unit 4. The detection circuit may be any circuit as long as it can detect an abnormality using a comparison check using duplication of arithmetic circuits, parity prediction, or the like. Since this fault detection becomes clear in the next cycle after data is written to the register file 1, the integrity of the data in the register file 1 is not guaranteed. However, in this example, in the recovery processing routine after a failure is detected, the contents are determined based on the information in the register 6 that stores the data in the register file 1 before the writing is performed, and the information in the register 7 that indicates the writing position of the data. Processing is performed to write back the register in the register file 1 into which the unguaranteed information has been written to normal data. By doing this, the state before the failure occurred is reproduced, and retry at the instruction level becomes possible. In addition, flip-flop 8
Based on the contents of register 9, it is determined whether there was a write to register file 1 in the previous step, and based on the contents of register 9, it is determined whether the instruction in which the failure occurred was the previous instruction. executed.

FIG. 2 is a schematic flowchart of the recovery processing routine. First, when the occurrence of a failure is detected in step 201,
In step 202, it is determined based on the contents of the register 6 whether or not the failure occurred in the previous instruction. If the failure occurred in the previous instruction, the process goes to step 203; otherwise, the process goes to step 207.

In step 203, it is determined based on the contents of the flip-flop 8 whether or not registers (general-purpose registers visible to software) are rarely rewritten in the cycle in which the failure occurred;
If it has been rewritten, in step 204 the contents of register file 1 are returned to the state before rewriting based on the information in register 6.7, and then the process goes to step 205. If it is determined in step 203 that the data has not been rewritten, the process goes directly to step 205. In step 205, before rewriting the general-purpose register, it is determined whether the instruction rewrites the information necessary for restarting the memory contents, etc., that is, whether the previous instruction can be restarted from the middle. If restarting is not possible, the abort is executed. The process is executed, and if it can be restarted, a retry is performed from the previous instruction in step 206. on the other hand,
If the process goes to step 207, it is determined whether or not the register file 1 has been rewritten, and if it has been done, the contents of the register file 1 are returned to the state before the rewrite in step 208, and then the process goes to step 209. If rewriting has not been performed, the process directly advances to step 209. In step 209, it is determined whether the command can be restarted from the middle,
If restart is not possible, abord processing is executed, and if restart is possible, the instruction is retried in step 210.

According to this embodiment, each time the data in the register file 1 is rewritten, the data written in the register file immediately before and the register position of this data are stored in the registers 6 and 7, so that the hardware The preserved information can be used to significantly increase the possibility of performing an instruction-level retry in the event of a failure;
It is possible to easily and quickly recover from a temporary hardware failure. Furthermore, since calculation and writing are performed in one cycle, even commands that require complex control can be executed easily and in a short time.

[Effects of the Invention] As described above, according to the arithmetic processing device of the present invention, computation and writing are performed in the same cycle, and information obtained one cycle before a hardware failure is preserved to be used when the failure occurs. This has the effect of making it possible to retry instructions and immediately avoid temporary hardware failures.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the arithmetic processing device of the present invention, FIG. 2 is a flowchart showing a recovery processing routine after a failure is detected, which is executed by the device shown in FIG. 1, and FIG. 4 is a block diagram showing an example of the relationship between the register group and the arithmetic unit of a conventional arithmetic processing device, FIG. 4 is a flowchart of an instruction retry routine in the device shown in FIG. 3, and FIG.
The figure is a block diagram showing another example of the relationship between the register group and the arithmetic unit of a conventional arithmetic processing device. 1...Register file 2.3...Multiplexer 4...Arithmetic unit 6.7...Register 8.9...Flip-flop agent Patent attorney Nori Chika Ken Yudo Sanno - Figure 2, Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] It was retained in the register file before being rewritten in an arithmetic processing unit that has a register file consisting of multiple registers that read and write data as instructions are executed, and retries instructions when a hardware failure is detected. A first register that holds information, a second register that holds register position information to which the information held in the first register was written, and whether data was written to the register file in the previous step. a flip-flop that indicates whether or not the register file has been rewritten; and when it is determined by the flip-flop that the register file has been rewritten, the data in the register file is returned to the state before the rewriting based on the contents of the first and second registers. 1. An arithmetic processing device comprising: control means for performing processing.