JPH0121517B2 - - Google Patents

Description

Detailed Description of the Invention The present invention stores audio data in which an encoded audio signal is divided into predetermined memory units in an audio memory device, reads out the audio data in memory units in the audio memory device, and reproduces it as audio. This system relates to a speech synthesis and playback system that synthesizes and plays back sentences by voice by specifying the arrangement of voice data, and in particular inputs and outputs data between control means such as a computer and storage means such as a voice memory device. This invention relates to a speech synthesis and playback system with an improved memory interface circuit.

Hereinafter, a conventional example will be explained based on the drawings. 1st
The figure is a block diagram showing a conventional example of a speech synthesis and playback system. In the figure, 1 is a computer for controlling speech playback, 2 is a system bus, and 3 is a communication unit that receives specifications of sentences to be synthesized from other devices. , 4 is a storage device in which a starting address table of each audio data in a memory unit stored in the audio memory device is stored, and 5 is a storage device that sends an address signal of a fixed length to the audio memory device starting from the starting address of the memory unit. 6 is an audio memory device, and in this example, there are three channels CH1, CH2, and CH3 that can be played simultaneously.
is provided. Furthermore, 7 is a reproduction device that reproduces encoded data outputted from the audio memory device into an analog signal, and 8 is a speaker for broadcasting.

In the above configuration, a command for specifying a sentence to be synthesized is sent from an external device (not shown) to the communication unit 3.
When the data is sent to the computer 1 via the system bus 2, the computer 1 refers to the end address table of the audio data stored in the storage device 4, and based on the command, outputs the audio data in each channel of the audio memory device. A control signal is sent to the memory interface circuit 5 to cause the playback device 7 to output data in a predetermined order. The memory interface circuit 5 sends address signals of a fixed length to the audio memory device 6 in a specified order for each channel of the audio memory device 6 based on the control signal. and each channel of the audio memory device 6
Audio data is output from CH1, CH2, and CH3 in the designated order to the playback device 7 corresponding to each channel, and the playback device 7 outputs these audio data as an analog audio signal by the playback speaker 8. .

For example, when performing the above-mentioned multiplex local broadcast using the above method, the beginnings of the words of the broadcast sentences of each channel remain aligned as shown in Figure 2 for time t, and the interval between the beginning of one word and the beginning of the next word remains the same. is constant. Therefore, the reproduced text loses the natural feel of the oral text, such as the pauses and accents, and has disadvantages such as the fact that broadcasts from adjacent platforms can be heard at the same time, making it difficult to read.

An object of the present invention is to provide a speech synthesis and reproduction system that can sequentially reproduce speech data for each memory unit into speech at time intervals according to word length.

To achieve the above object, the present invention provides an audio memory device in which audio data obtained by dividing an encoded audio signal into predetermined memory units is stored, and an address of the audio data stored in the audio memory device. a storage device storing information and reproduction time information regarding the unit reproduction time required to reproduce the audio data of each memory unit and the total reproduction time required to reproduce the specific audio data group; and the content designation signal of the broadcast text. a control means for outputting a control signal for sequentially reading address information and playback time information of specific audio data from the storage device in each memory unit based on a reproduction end flag signal; addressing means for fetching address information of specific audio data from a storage device and sequentially proceeding with addressing of the specific audio data in the audio memory device; playback time regulating means that receives unit playback time information, measures time in synchronization with address designation, and instructs the address designation means to stop the progress of address designation when the measured time matches the unit playback time of specific audio data; and receives total playback time information of a specific audio data group from the storage device according to the control signal, and measures time in synchronization with address designation, and when the measured time matches the total playback time of the specific audio data group. a reproduction end flag signal generation means for outputting a reproduction end flag signal to the control means; a reproduction means for sequentially reproducing the audio data at the address specified by the address specifying means into audio;
This constitutes a speech synthesis and playback system comprising:

A first embodiment of the present invention will be described based on FIGS. 3 and 4. FIG. 3 is a block diagram showing the configuration of a speech synthesis and reproduction system according to the present invention. FIG. 4 shows a specific circuit configuration of the memory interface circuit 20 shown in FIG. 3, in which 9 is an instruction decoder, 10 and 11 are latch circuits, 12 is a presetable up counter, 1
3 is a presettable down counter, 14 is an all-zero detection circuit, 15 is an inverter, 16, 17
is an AND gate, CLK is an audio sampling signal,
18 is a reproduction end flag signal, and 18 is an audio memory address bus. Here, the latch circuit 10 and the up counter 12 constitute address designating means, the latch circuit 11, the down counter 13, the all-zero detection circuit 14, the inverter 15, and the AND gate 16 constitute reproduction time regulating means, and the latch circuit 11, The down counter 13 and the all-zero detection circuit 14 constitute reproduction end flag signal generation means.

The operation of the speech synthesis and reproduction system according to the present invention in the above configuration will be described below. In the storage device 4, the start addresses of the audio data W ₁ , W ₂ , W ₃ . A table (Figure 5) is provided.

The computer 1 receives a specification of the content of the broadcast message from an external device (not shown) via the communication unit 3, refers to the table in the storage device 4 according to this specification, and
The start address is written in latch 10 of memory interface circuit 20, the word length is written in latch 11, and these values are preset in counters 12 and 13, respectively. Here, the contents of the broadcast message received by the computer 1 include, for example, in the case of a station announcement, the sentence types include approach announcement, arrival announcement, and departure announcement, and include the train type, destination, own station name, platform number, Specifications such as time are added.

Furthermore, the computer 1 opens the gate 17 through the command decoder 9 in the memory interface circuit 20 via the system bus 2, and starts the counters 12 and 13 with the audio sampling clock signal CLK.
As a result, the presettable up counter 12 sequentially accesses the audio memory device 6 at the sampling clock speed from the head address of the desired audio data, and broadcasting is performed from the speaker 8 via the playback device 7.

Meanwhile, the down counter 13 which can be preset during this time
is subtracting the preset value, and when the counted value becomes zero, the all-zero detection circuit 14 operates, closes the gate 16, stops the counting operation of the counters 12 and 13, and also sends the desired audio to the computer 1. A flag signal 18 is issued to report the end of reproduction.

Note that in the computer 1, the address word length data of the next memory unit of audio data to be uttered following the memory unit of audio data currently being uttered can be written into the latches 10 and 11 before receiving the flag signal 18. After receiving the audio data, the process of uttering and reproducing the next memory unit of audio data is completed in a short time.

According to the configuration of this embodiment, if words including pauses in actual dictation are recorded and encoded as memory units and stored in the voice memory device 6, the voice data in each memory unit can be stored in each memory unit. Since the audio is played back according to the length of the playback time, the natural feel of the sentences, such as pauses and accents, will not be lost even if the sentences are composed and uttered according to the content. Since it is only necessary to output a control signal for sequentially reading out the playback time information for each memory unit, the increase in the burden on the software of the computer 1 is extremely small compared to the conventional example shown in FIG.

As described above, since the increase in software burden is small, multiplex broadcasting is also possible, and a specific example thereof is shown in FIG. In FIG. 6, 21 is a memory data bus, and 22 is a reproduction channel selector.

When performing multiplex broadcasting with this configuration, the computer 1 transfers the start address data and word length data (playback time data) of audio data in memory units for each playback channel to a memory interface circuit provided corresponding to each playback channel. The instruction decoder 9 provided in the memory interface circuit 20 instructs the playback location in sequence. As a result, the address signals sent by each memory interface circuit 20 to the memory address bus 19 do not overlap in time, and therefore the memory data bus 21
The audio data of each channel is sequentially output. Here, based on the control signal from the computer 1, a signal is given from the reproduction channel selector 22 to the reproduction device 7 of each channel to instruct the reproduction device 7 to take in data from the memory data bus 21, thereby performing reproduction in synchronization with each memory interface circuit 20. becomes possible. Therefore, the memory interface circuit of the speech synthesis and reproduction system according to the present invention can realize audibly asynchronous multiplex broadcasting of the audio sentences reproduced from the reproduction device 7 of each channel without impairing the sense of naturalness.

Now, when observing the speech waveform, it consists of a voiced section and a following unvoiced section, as shown in Figure 7.

When audio is encoded and stored in an audio memory device, the memory capacity can be reduced by about 30% by removing unvoiced sections and storing only voiced section data, compared to storing data as is. When reproducing normal speech sentences, that is, with natural accents, pauses, etc., from a voice memory device that stores voiced interval data (hereinafter referred to as voiced interval data), the memory interface circuit stores voiced interval data. Any device may be used as long as it has a function of stopping the address progression when the reproduction of the entire audio unit is completed and a function of reporting the completion of reproduction of the entire audio unit to the computer 1. A specific example of a memory interface circuit having the above functions will be explained based on FIGS. 8 to 11.

The configuration of the embodiment shown in FIG. 8 differs from the embodiment shown in FIG. 4 in that a latch 23, a down counter 24, and an all-zero detection circuit 25 are added. In this embodiment, the storage device 4 (FIG. 3) stores three data tables as shown in FIG. 9: the start address of the memory unit, the length of the voiced part, and the total length including the unvoiced part and the voiced part. There is.

In the above configuration, the computer 1 gives the start address to the latch 10, the voiced length to the latch 11, and the total length of the audio data to the latch 23, and then presets the respective values to the counters 12, 13, and 24. Then, the gate 17 is opened and the counters 12, 13, and 24 are activated. Then, by the same operation as already described in the explanation of FIG.
2 and 13, the counter 2 continues even after the voiced part has finished playing.
4 continues the counting operation, and after a predetermined period of time has elapsed, the all-zero detection circuit 25 operates and generates a reproduction end flag signal 18 for the required audio memory unit to the computer 1.

As described above, by providing a means for counting the total length (total playback time) of audio data in a memory unit, it is possible to store only valid audio data in the audio memory device 6, and it is possible to play back without impairing naturalness. Become.

A similar effect can also be achieved by the memory interface circuit shown in FIG. In the figure, numerals 26 and 27 are gates newly provided in the embodiment of FIG. In this embodiment, the storage device 4 (FIG. 3) is provided with a table containing data such as the start address of a memory unit of audio data, the length of a voiced portion, and the length of an unvoiced portion, as shown in FIG. The computer 1 (FIG. 3) presets the unvoiced portion length value in the counter 24 via the system bus 2 and the latch 23, opens the gate 26 in response to the voiced portion reproduction end detection signal from the all zero detection circuit 14, and starts the counter 24. The all-zero detection circuit 25 generates a flag signal 18 indicating the end of the silent period, that is, the end of reproduction of the audio data in the desired memory unit.

Now, using the memory interface circuit shown in FIGS. 8 and 10 in a speech synthesis and playback system,
In the case of multiplex broadcasting, when the playback device is synchronized by a playback channel decoder as in the embodiment shown in FIG. During the reproduction time of the silent portion, it is necessary to stop the reproduction channel selection signal, which places a large burden on the software.

Therefore, when multiplex broadcasting is performed by storing only voiced portions of audio data in an audio memory device as described above, each memory interface circuit provided corresponding to each playback channel itself starts and stops the corresponding playback device. By configuring the system to issue commands, the burden on the software can be reduced.

Next, FIG. 12 shows an embodiment of a memory interface circuit configured to issue commands to start and stop a corresponding playback device by itself. In this embodiment, the output of the all-zero detection circuit 14 shown in FIG. 8 is sent through the inverter 15' to the function stop signal 28 of the corresponding playback device, so that the output of the all-zero detection circuit 14 is at a high level, that is, the voiced part. The feature is that the playback device is configured to permit data capture while the playback continues. The overall structure of a multiplex broadcasting audio synthesis and playback system to which the above memory interface circuit is applied is as shown in FIG. The only difference is that the memory interface circuit 29 is configured to send the function stop signal 28 to the playback device 7 as described above, and the other configurations are the same as in FIG.

In the above configuration, the reproduction channel selector 22
The data capture command signal is output from the memory unit until the playback of the entire audio data in the memory unit is completed.
The function stop signal 28 is output from the memory interface circuit 29 to the playback device 7 of the channel where the playback of the audio portion of the audio data has been completed, so the output of the playback device 7 becomes zero and the unvoiced portion of the audio data is expressed. Can be done. Therefore, only by instructing the memory interface circuit 29 to start the reproduction of the computer 1, the voiced part and the unvoiced part of the audio data are reproduced, and the increase in the burden on the software is reduced.

The above method can be performed in exactly the same way even when the memory interface circuit shown in FIG. 10 is applied.

Alternatively, exactly the same effect can be obtained by inputting a zero value to the reproducing apparatus using the function stop signal 28 from the memory interface circuit during the silent section of the audio data without starting or stopping the reproducing apparatus itself. Such a circuit itself can be easily realized, and its explanation will be omitted here.

By the way, when the computer 1 executes the audio playback control job, it is necessary to process interrupts from other peripheral devices such as the communication unit 3, and for this purpose, it is necessary to write new data into each latch or start a counter. A delay in this is not desirable because it impairs the quality of the reproduced voice or the naturalness of accents, pauses, etc.

Another embodiment of the memory interface circuit for preventing the above problem is shown in FIG. In the figure, 30 is a latch, and 31 is a decoder that generates a playback end notice interrupt signal IRQ to the computer 1 when the value of the counter 13 becomes less than a predetermined value. A decoder having such a function can be easily realized using, for example, a read-on memory.

In the above configuration, if an interrupt with a lower priority than the interrupt signal IRQ occurs to computer 1 from another,
If a predetermined value is preset in the decoder 31 according to the recovery time from the interrupt handling routine, the next memory unit of audio data can be written into each latch and the counter can be filled in before the end of the playback of the audio data in the memory unit. , it is possible to prevent the effect on the naturalness of the sound quality or pause during playback.

Note that even in normal processing, if it is preferable to prepare the next memory unit of audio data that has already been written in the latch before the end of playback of the audio data in the memory unit, the latch 30
It is sufficient to always enter a constant value in .

Next, when the end notice interrupt signal IRQ is generated from the memory interface circuit for saving the memory capacity of the audio memory device shown in FIGS. 8 and 10 before the end of the reproduction of audio data in a memory unit, The decoder 31 may detect that the value of the counter 24 has become less than or equal to a predetermined value.

As explained above, according to the present invention, since the audio data in each memory unit is reproduced as audio at the playback time unique to each memory unit, the audio data group in each memory unit is used as a broadcast sentence to give an aurally natural feeling. can be played back into audio without any loss.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional speech synthesis and playback system, FIG. 2 is an explanatory diagram showing the form of audio data output from the audio memory device 6 of FIG. 1, and FIG. 4 is a block diagram showing an embodiment of the speech synthesis and playback system. FIG. 4 is a diagram showing a specific circuit configuration of the memory interface circuit 20 in FIG. 3. FIG. 5 is a diagram showing the specific circuit configuration of the memory interface circuit 20 in FIG. Figure 6 showing a table showing the memory contents of
The figure is a block diagram showing an example in which the memory interface circuit of Fig. 4 is applied to an audio synthesis and playback system for multiplex broadcasting, Fig. 7 is a diagram showing audio waveforms, and Fig.
9 is a circuit diagram showing another embodiment of the memory interface circuit, and FIG. 9 is a diagram showing a table stored in the storage device 4 when the memory interface circuit of FIG. 8 is applied to a speech synthesis and playback system.
FIG. 10 is a circuit diagram showing another embodiment of the memory interface circuit, and FIG. 11 shows a table stored in the storage device 4 when the memory interface circuit of FIG. 10 is applied to a speech synthesis and playback system. 12 is a circuit diagram showing still another embodiment of the memory interface circuit, FIG. 13 is a block diagram showing an example in which the memory interface circuit of FIG. 12 is applied to a speech synthesis and playback system, and FIG. 14 FIG. 7 is a diagram showing still another embodiment of the memory interface circuit.

Claims (1)

[Claims] 1. An audio memory device in which audio data obtained by dividing an encoded audio signal into predetermined memory units is stored, address information of the audio data stored in the audio memory device, and each memory unit. a storage device that stores playback time information regarding the unit playback time required to play back the audio data and the total playback time required to play back a specific audio data group; control means for outputting a control signal for sequentially reading address information and playback time information of specific audio data from the storage device based on the memory unit; Addressing means that takes in address information of audio data and sequentially advances addressing of specific audio data in the audio memory device;
Receives unit playback time information of specific audio data from the storage device in response to a control signal from the control means and measures time in synchronization with address designation, and when the measured time matches the unit playback time of the specific audio data; a reproduction time regulating means for instructing the addressing means to stop the progress of addressing; a reproduction end flag signal generating means for outputting a reproduction end flag signal to the control means when a time coincides with the total reproduction time of a specific audio data group; and a reproduction end flag signal generating means for outputting a reproduction end flag signal to the control means; A speech synthesis playback system comprising: a playback means for playback. 2. In the speech synthesis playback system as set forth in claim 1, the playback time for time monitoring of the playback time regulating means is the sound part playback time required to play voiced part data of specific sound data. A speech synthesis playback system characterized by being set to.