JPH01220438A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to improvement of a polycrystalline silicon film used as a mask for ion implantation.

[Conventional technology]

Taking a conventional MO3 type semiconductor device as an example, a manufacturing method thereof will be explained step by step.

First, as shown in FIG. 2 (al), a field oxide film 2 is formed on one main surface of a semiconductor substrate 1 for the purpose of isolating each element, and then a gate oxide film 3 is formed using a thermal oxidation method. 4,500 polycrystalline silicon films 4, which will become gate electrodes, are produced by vapor phase growth.

Next, in order to lower the resistance of this polycrystalline silicon film 4, impurities such as phosphorus 5 are added to the polycrystalline silicon film 4 at approximately 900°C.
The sheet resistance value of the polycrystalline silicon film 4 is made approximately 25 Ω/D by thermal diffusion at a temperature of .

Next, as shown in FIG. 2(b), the polycrystalline silicon film 4 and gate oxide film 3 are etched using the resist as a mask to expose the portions that will become the source/drain regions of the semiconductor base Fi1, and the resist is removed. . Next, using the polycrystalline silicon film 4 serving as the gate electrode and the field oxide film 2 as masks, an impurity 6 having a conductivity type opposite to that of the semiconductor substrate 1 is implanted into the source/drain regions using ion implantation technology.

Thereafter, as shown in FIG. 2(C), heat treatment is performed at a temperature of about 900° C., so that the implanted impurity 6 is diffused to a predetermined depth in the semiconductor substrate 1, and the source
A drain layer 7 is formed. Next, an interlayer insulating film 8 is formed,
A contact hole 9 is opened, and an aluminum wiring 10 is further provided.

[Problem to be solved by the invention]

As described above, in the conventional technique, after forming the polycrystalline silicon film 4 that will become the gate electrode, impurities 5 are diffused into the polycrystalline silicon film 4 by thermal diffusion in order to lower the resistance value. At this time, the polycrystalline silicon film 4 is formed by the vapor phase growth method at a temperature of about 400"C to 450°C, but the polycrystalline silicon film 4 in the formed state is not crystallized, and the silicon Atoms exist randomly in the polycrystalline silicon Wid.In order to lower the resistance value of the polycrystalline silicon film 4 in this state, impurities such as phosphorus 5 are added to the polycrystalline silicon film 4 at a temperature of about 900°C. When thermally diffused, the polycrystalline silicon film 4 becomes a collection of silicon single crystal lumps (grains) 1) of a certain size (for example, around 0.5 μm in diameter) as shown in FIG.

These grains 1) become larger as the concentration of impurities thermally diffused into the polycrystalline silicon film 4 increases, and in some regions only one grain 1) exists in the thickness direction of the polycrystalline silicon film. become. One grain 1) is a silicon single crystal, and each grain 1) has a different silicon single crystal plane orientation.

Therefore, when implanting the impurity 6 of the opposite conductivity type to the semiconductor substrate 1 into the source/drain region using ion implantation technology,
Grain 1 with surface orientation that is easy to penetrate (channeling)
) The impurities 6 implanted into the polycrystalline silicon film penetrate deep into the polycrystalline silicon film, and some of them reach the channel portion which is the surface of the semiconductor substrate 1.

When the source-drain distance was wide (for example, 2.0μ or more) like in previous MO3 type transistors, this did not pose a problem because the amount of impurity 6 that reached the channel was small, but recently MO3 type transistors Source of
As the drain spacing has become smaller (for example, 2.0μ or less), the influence of the minute amount of impurity 6 that has reached the channel region becomes greater, causing problems such as variations in the electrical characteristics such as the threshold voltage of MO3 transistors. is coming out.

This invention was made in order to solve the above-mentioned problems, and is a semiconductor device that can prevent penetration caused by ion implantation, thereby making it possible to manufacture MO3 type semiconductor devices with stable electrical characteristics. The purpose is to obtain a manufacturing method.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention includes a step of performing ion implantation using a polycrystalline silicon film as a mask, after forming an insulating film on one main surface of a semiconductor substrate, and then depositing a first polycrystalline silicon film thereon. a first step of forming a polycrystalline silicon film; and a second step of forming a second polycrystalline silicon film on the first polycrystalline silicon film after thermally diffusing impurities into the first polycrystalline silicon film.
and the step of the above insulating film and the first step. This method consists of a third step of patterning the second polycrystalline silicon film and then implanting impurity ions using these films as a mask.

[Effect]

In this invention, an upper polycrystalline silicon film without impurities is formed on a lower polycrystalline silicon film with impurities diffused, and then ions are implanted using these polycrystalline silicon layers as masks. It is possible to improve the mask effect during implantation and prevent penetration due to ion implantation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view for explaining the manufacturing method of a semiconductor device according to an embodiment of the present invention in the order of steps. In the figure, the same reference numerals as in FIG. The first polycrystalline silicon film 13 is a second polycrystalline silicon film formed on the film 12.

Next, the manufacturing method will be explained.

Similar to the conventional technique, a field oxide film 2 is formed on one main surface of a P-type silicon substrate 1 for the purpose of isolating each element, a gate oxide film 3 is formed by thermal oxidation, and then a gate oxide film 3 is formed by thermal oxidation. Approximately 2000 first polycrystalline silicon films 12, which will become part of the gate electrode, are produced. Next, approximately 90% of phosphorus was added to the polycrystalline silicon film 12 in order to lower the resistance of the gate electrode.
Thermal diffusion occurs at a temperature of 0°C. In this thermal diffusion, the film thickness is 2000
The resistance value of the human polycrystalline silicon film 12 was about 30Ω/D.

Next, on the polycrystalline silicon film 12 in which phosphorus 5 has been thermally diffused, a second polycrystalline silicon film 13 of about 2,500 layers is further formed at a temperature of about 420° C. by the same vapor phase growth method. Since the temperature at which this polycrystalline silicon film 13 is generated is as low as 420°C, almost no phosphorus 5 that has already diffused into the polycrystalline silicon film 12 is diffused, and almost no phosphorus exists in the upper polycrystalline silicon film 13. I haven't.

Next, as shown in FIG. 1(b), as in the prior art, the first polycrystalline silicon film 12 and gate oxide film 3 are etched using a resist as a mask.
Portions of the semiconductor substrate 1 that will become source/drain regions are exposed, and the resist is removed. After that, using the upper second polycrystalline silicon film 13 and field oxide film 2 as a mask, ion implantation technique is used to inject arsenic 6 into 50 keys.
Inject 4×10 lS/cd with an energy of .

Next, as shown in FIG. 1(C), 9
The implanted arsenic is diffused by heat treatment at a temperature of 00° C. for 40 minutes, and the source/drain layer 7 is formed.

After that, the glabella insulating film8. Contact holes 9 and aluminum wiring 10 are formed.

Regarding the resistance of the gate electrode, due to the heat treatment at 900° C. for 40 minutes when forming the source/drain layer 7, the phosphorus 5 present in the lower first polycrystalline silicon film 12 is transferred to the upper second polycrystalline silicon film 12. 1)! 13, the heat is sufficiently diffused,
In the final finished state, it is 25Ω, which is almost the same as the conventional technology.
/D was obtained.

In the MO3 type semiconductor device manufactured as described above, after the upper polycrystalline silicon film 13 is formed, the source
The temperature of the heat treatment up to the ion implantation for forming the drain layer 6 is the highest temperature of 420° C. when the upper polycrystalline silicon film 13 is formed by vapor phase growth.

At this temperature, impurities such as phosphorus in the lower polycrystalline silicon film 12 hardly diffuse, and the upper polycrystalline silicon film 13 has amorphous silicon atoms randomly existing in the source/drain layer. Since it can be used as a mask for ion implantation to form 6, impurity ions are less likely to penetrate locally into the channel region as in the prior art.

Figure 4 shows the threshold voltage (Vto
) is shown using the implantation energy of arsenic ion implantation to form the source/drain layer as a parameter.

In the case of the conventional technique, the solid line 14 is a solid line, but according to the present example, the line is a dotted line 15, which shows that it is effective in preventing ions from penetrating into the channel portion due to ion implantation.

In the sample shown in FIG. 4, the arsenic ion implantation for forming the source/drain layers was 4×10,”/cIa.
I went there. Also, the threshold value for one parameter, that is, one implantation energy, is 500 to 700 MO3.
The VtU of the type transistor was measured and the average value is shown. Further, the MO3 type transistor has a source-drain interval of 1.2 μm and a source-drain width of 20 μm.

As described above, according to this embodiment, a second polycrystalline silicon film in which impurities are not diffused is formed on a first polycrystalline silicon film in which impurities are diffused, and then these polycrystalline silicon films are masked. Since ion implantation is performed to form sources and drains, the masking effect of the polycrystalline silicon film can be improved and penetration caused by ion implantation can be prevented.

In the above embodiment, an N-channel MO3 type transistor using a P-type silicon substrate and arsenic implanted into the source and drain was shown, but it goes without saying that a P-channel MO3 type transistor may also be used. (The impurities to be implanted may also be other impurities such as boron or phosphorus, although there are differences in degree, and the same effect can be obtained in this case as well.

In addition, in the above embodiment, the source of the MOS transistor
Although the case of ion implantation for drain formation has been described, the present invention can be applied to any method in which impurity ions are implanted using a polycrystalline silicon film as a mask, and in this case, the same effect as in the above embodiment can be obtained. play.

〔Effect of the invention〕

As described above, according to the method for manufacturing a semiconductor device according to the present invention, after forming an upper polycrystalline silicon film in which impurities are not diffused on a lower polycrystalline silicon film in which impurities are diffused, Since ions are implanted using the polycrystalline silicon layer as a mask, the mask effect during ion implantation can be improved and penetration caused by ion implantation can be prevented, and as a result, a semiconductor device with good electrical characteristics can be manufactured.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention in step 1), and FIG. 2 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device in the order of steps. A cross-sectional view, FIG. 3 is a diagram for explaining problems in the conventional method, and FIG. 4 shows the relationship between the threshold voltage of a MOS transistor and the impurity implantation energy for forming the source/drain layer. It is a diagram. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Gate oxide film, 5... Phosphorus impurity, 12
...first polycrystalline silicon film, 13...second polycrystalline silicon film. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a method for manufacturing a semiconductor device, which includes a step of selectively forming a polycrystalline silicon film on a semiconductor substrate and performing ion implantation using this as a mask, the step includes forming an insulating film on one principal surface of the semiconductor substrate. A first step of forming a film and then generating a first polycrystalline silicon film thereon; and after thermally diffusing impurities into the first polycrystalline silicon film.
a second step of forming a second polycrystalline silicon film on the first polycrystalline silicon film, and masking these films after patterning the insulating film and the first and second polycrystalline silicon films. and a third step of ion-implanting impurities.