JPH01221925A - Variable length code conversion method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a variable length code conversion method applied to the transmission or recording of digital signals.

[Conventional technology]

Various code conversion methods have been developed for use in recording and reproducing digital signals on optical disks, magnetic disks, etc. as recording density increases. The following three points are particularly required as properties for this code.

(1) Minimum magnetization reversal interval T.

It is desirable that T m I a be large in order to avoid the influence of band limitations of the recording/reproducing system.

(2) Maximum magnetization reversal interval T1.8 In order to extract clock information in order to obtain a self-clock function, it is desirable that T m @X be small.

(3) Detection window width Tw Represents the degree of margin against time axis fluctuations such as jitter of the reproduced signal and peak shift due to waveform interference, and is preferably large.

From (1) and (3), there is also an evaluation method that states that the larger T□, x'1'', the better.

When converting an m-bit data word to an n-bit code word,
Assuming that the minimum value of the number of runs of "O" between "l" and "1" in the code word is d1 and the maximum value is k, these are expressed as follows.

T. = (d+1)T.

To, = (k+1)T, # Tv = (m/n)T (T: 1-bit length of data word) Conventionally, various code conversion methods have been devised from the above viewpoint, and representative ones include MFM, (2°7) RLL is mentioned. These are code conversion methods with the following values: Note that from now on, for convenience, it will be standardized and represented by T.

MFM T1. =1. OT□,=2.0'rw=o, 5 T1. XTw=0.5(
2,7) RLL T1. =1. 5 7. ,,=4. 0TVF
=0. 5'r0. xTv=Q,
75 [Problem to be solved by the invention] However, as recording density increases, the minimum magnetization reversal interval T m
l n or T1. A code conversion method with larger xTw has become necessary.

Means for Solving Problem c] The present invention provides a minimum data length m = 2, a minimum codeword length n = 5, a codeword length number r m −x = 6, and a binary system in which codewords after conversion are connected to each other. This realizes a variable length code in which the minimum value d of the number of runs of "0" between "1" and "1" in a code word string is 4, and the maximum value is 19, and T1. =2.0,T,,,=8.
0, Tw=0.40, T1. It has the characteristic of xTw =0.80.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. The condition for being able to use it as a code word in a variable length code is M
FIG. 3 is a diagram showing a pattern of bit code words. In FIG. 1, (1) the (d, k) restriction is satisfied within one code word.

(2) Even if codewords are connected, the (d, k) restriction is satisfied.

(3) Codeword boundaries can be correctly determined, and decoding can be performed at will.

Next, a method of constructing a code word that satisfies these conditions will be described. However, for convenience of explanation, the code word that satisfies (1) is (d,
k) Restricted codewords, codewords that satisfy (1) and (2) are valid codewords (1), (2).

(3) A codeword that satisfies all of the above is called a unique codeword.

D, T, Tang and L, R, Bahl,
”Block Codes for Class of
Con5trained No1seless Cha
“nnels”.

Information and Control,
According to Vol. 17.1970, (d
, k) It has been proven that the number of code words N (n) of the restriction code can be found by the following equation.

N(n)=n+1 (1≧n≧d+1)N(n
) =N (n-1) +N (n-d-1)(d+1
<n≦k) N(n)= (+1-n to d+) +N(n-i-1) (k<n≦(1+k) N(n)=N (n-i-1) (n>d (10k) However, N(n)=O(Neo) N(0)=1.

As a result, the total number of n-bit (d, k) restricted code patterns shown in FIG. 1 can be calculated.

In addition, in order to satisfy condition (2), the length of L block is p
It is sufficient that the length q of the 1R block satisfies the following equation.

dO≦p≦k.

d1≦q≦k1 (dO+dl =d, kO+kl =k) In the effective codewords configured in this way, the (d, k) restriction will not be violated even if the codewords are connected.

These n-bit effective code words are dO, di, ko.

R blocks and L blocks can be obtained by appropriately giving kl and selecting codewords that satisfy this condition from (d, k) restricted codes.

Next, rules for selecting unique code words will be explained. Second
As shown in the figure, if the 2n-bit code word A and the n-bit code words B and C connected are equal, decoding becomes impossible. Therefore, such codeword A is not a unique codeword. In general, an rn-bit unique codeword is obtained by removing from the rn-bit effective codeword an rn-bit effective codeword obtained by concatenating unique codewords smaller than rn bits. Assuming that the number of effective codewords of rn bits is Nr and the number of unique codewords is Vr, when r=1, all effective codewords are unique codewords. The number of code words is Vl = N1. When r = 2, the number of code words is V2 = N2-VI

The number of code words is V3 = N3- (Vl”+V1 xV22+V2 x
The same applies to the case where V1') r=4 or more.

For the case of dO=0, d1=4, kO=4, kl=15, the code words thus obtained are shown in Table 1, and the number of code words is shown in Table 2.

Table 1 (10θ110) 010000010000000
(101101) 00, 00OOQOOOOOOOO
(1111101000) 0OO0, 00E
I0, 00O0, 00O0, 00OOO (111111
010000), 0100000010000
10000100000100000 (1111111
11100) 0100001000'00010
000010000000000 (111111111
110) 0100OOOIOJ) 001000
01000000000000oootoooooooo
ooooooooooooooooooooooo
ooooooooooooooooooooooooooooo0
100001000010dOOOO0, 000000
00000100001 [1000001000010
0000000000 Table 2 Next, data words are assigned to the code words obtained in this way. When r=1, since the data word is 2 bits, the required number of 5-bit unique code words (hereinafter referred to as the required number of words) is 4. However, as shown in Table 2, the number of unique code words is 1, so for example, only "00n" is assigned.

There will be a shortage of three guardian words.

If r=2, the 3 not allocated at r=1
2 data words “01”, “10”, “11”
12 4-bit data words created by adding bits to 1
Assigned to a unique codeword of 0 bits, which is 5
There are only 7 pieces, so 7 pieces are missing.

Similarly, in the case of r=3, 28 6-bit data words obtained by adding 2 bits (4) after the 7 data words that were not allocated in r=2 are combined into a 15-bit unique code word. Assign to There were only 15 of these i1
Three pieces are missing.

Repeat the same process for r = 4 or more. Then, r = 6
In this case, the required number of words is 84, but the number of code words is 117, and all data words can be allocated. The words in parentheses in Table 1 are examples of assigned data words. As a criterion for selecting 84 out of 117, priority is given to selecting code words in descending order of the number of "1"s in order to reduce the average magnetization reversal interval.

FIG. 4 is a diagram showing an example of an encoding circuit for realizing an embodiment of the present invention. The input data bit string is taken into a 12-bit shift register and sent to a latch circuit. Furthermore, these 12 bits are sent to a code conversion circuit. In the code conversion circuit, the first two bits out of the 12 bits are
When the r (1≦r≦6) bit is equal to any of the 2r bit data words in Table 1, the corresponding code word is sent to the parallel-to-serial conversion circuit. The serially converted code word is NRZ I
The signal is sent to a modulation circuit and subjected to NRZ I modulation. Further data strings are loaded into the shift register by the number of bits in the matched data bit string, and the same process is repeated.

FIG. 5 shows an example of a decoding circuit for decoding the signal encoded by the encoding circuit of FIG. 4. The input codeword bit string is taken into a 30-bit shift register and sent to a latch circuit. Furthermore, these 3
The 0 bit is sent to the sign inversion circuit. In the code inversion circuit, when 5r (1≦r≦6) bits from the beginning among the 30 bits are equal to any of the 5r-bit code words in Table 1, the corresponding data word is sent to the parallel-to-serial conversion circuit. . However, in this case, matching is performed with priority given to the code word with the longest length. That is, first it is checked whether it is a 30-bit codeword, then it is checked whether it is a 25-bit codeword, and finally it is checked whether it is a 5-bit codeword. If it is equal to any of the code words in Table 1, the corresponding data word is sent to the parallel-to-serial conversion circuit. As many as the number of bits of the matched codeword,
Furthermore, the code word bit string is taken into the shift register and the same process is repeated.

[Other Examples]

Code words can also be constructed with rffi, , = 6 for the following parameters. They all have the same characteristics.

(a) dO=o, dl=4, kO=5, kl=1
4(b) do=o, dl=4, ko=11, kl
= 8 (c) do = 0, dl = 4, ko = 10,
kl = 9(d)dO・1, dl = 3, kO=
5, kl = 14 (e) do = 1, dl = 3, kO =
6, kl = 13 (f) dO = 1, dl = 3, kO
= 11, kl = 8 (g) dO = 1, dl = 3, kO =
12, kl = 7 (h) do = 2, dl = 2, k
O=6, kl=13(i)do・2, dl=2,
kO=7, kl=12(j)do=2, dl=2
,ko=12,kl=7(k)do=2,dl
=2, ko=13, kl = 6(1) do=3
, dl = 1, ko = 7, kl = 12 (m) do = 3,
dl = 1, kO = 8, kl = 11(n) dO: 3
, dl=1, kO=13, kl=6(o) dΩ=3
, di = 1, kO = 14, kl = 5(p)d
o=4, dl;0, kO=8, kl=11
(q) do・4, dl−0, kO−9, kl=10(
r) dO=4, di=0, kQ=14, kl
= 5(S) dO=4, dl =0, kO=
15, kl; 4 [Effects of the Invention] As explained above, the variable-length code conversion method of the present invention limits the number of 0'' runs at the start and end of a code word, and - allows for arbitrarily decodable code words. By choosing Waveform interference can be reduced in high-speed transmission, etc., and the practical effect is very high.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a pattern of an n-bit code word. FIG. 2 is a diagram illustrating uniquely decodable code words. Figure 3(a)
, (b) is a diagram illustrating non-unique codewords. FIG. 4 is a diagram showing an example of a block diagram of an encoding circuit. FIG. 5 is a diagram showing an example of a block diagram of a decoding circuit. 10.20・Salary・・・・Shift register 11.21・
・・・－・・・Latch circuit

Claims (2)

[Claims] (1) When the minimum data word length is 2 bits and the minimum code tone is 5 bits, variable length code conversion converts a 2r bit data word into a 5r bit code word for r where 1≦r≦6 In the method, “0” between “1” and “1” of a binary code bit string generated by the connection of code words after conversion
” to limit the number of runs to 4 or more and 19 or less, d0,
d1, k0, k1 as d0+d1=4, k0+k1=19
When it is a non-negative integer that satisfies, the number of runs of “0” at the starting end of one code word p is d0≦p≦k0, and “
A variable length code conversion method characterized in that the number of runs q of 0'' is limited to d1≦q≦k1. (2) The variable-length code conversion method according to claim 1, characterized in that the codewords are assigned to the data words with priority in descending order of the number of runs of "1".