JPH0122736B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device.

Complementary type generally used in semiconductor integrated circuit devices, especially master slice type gate array LSI
As shown in FIG. 1, the gate array of a MOS transistor integrated circuit device includes an input/output circuit 2 connected to the LSI external circuit, an input/output circuit 2 connected to the LSI external circuit, and an input/output circuit 2 connected to the LSI external circuit around the silicon chip 1, as shown in FIG. An internal circuit 3 is an assembly of internal logic functional elements in which gates are arranged in an array and wired with a first layer of aluminum and a second layer of aluminum formed on the internal gates via an insulating layer. Wiring areas are provided adjacent to the upper and lower sides of the internal circuit 3.

The internal circuit 3 has a plurality of complementary MOS transistors each consisting of a P-channel MOS transistor and an N-channel MOS transistor, and
A plurality of logical functional elements are configured according to a desired number of these plurality of logical functional elements to form an aggregate of these logical functional elements.

In the internal circuit 3 configured in this way, the wiring of the P-channel MOS transistor and the n-channel MOS transistor in the logic functional element, and the wiring between the logic functional elements are usually the P-channel MOS transistor and the n-channel MOS
Wiring is performed using an aluminum layer formed on the gate electrode of the transistor with an insulating layer interposed therebetween.

By the way, since the above-mentioned wiring inevitably has a portion where it intersects due to its structure, a structure as shown in FIGS. 2 and 3 has conventionally been adopted. Figure 2 is a top view of the part where the wiring of the internal circuit 3 intersects, and Figure 3 is the top view of the part where the wiring of the internal circuit 3 intersects.
The figure is a cross-sectional view, and in the figure, 4, 5, and 6 are P-type impurity diffusion regions that become active regions that are drains or sources formed in the n-type semiconductor layer 7;
9 is a gate electrode provided on gate regions 10 and 11 formed between these P-type impurity diffusion regions 4, 5, and 6, and 12, 13, and 14 are drains or sources formed in the P-type semiconductor layer. N-type impurity diffusion regions 15 and 16 serving as active regions are gate electrodes provided on gate regions formed between these n-type impurity diffusion regions 12, 13, and 14. Complementary type
The gate electrode 9 and the gate electrode 16 form a pair to form a complementary MOS transistor.
It constitutes a MOS transistor. 17
to 25 are P-type impurity diffusion regions 4, 5, 6, n
17 is a wiring made of a first layer of aluminum formed on the type impurity diffusion regions 12, 13, 14 and gate electrodes 8, 9, 15, 16 via an oxide film 26, which is an insulating layer. Positive power supply lines 18, 19, 20, 21 are signal lines located on the P-type impurity diffusion regions 4, 5, 6, 22, 23,
24 is a signal line located on the n-type impurity diffusion regions 12, 13, and 14, and 25 is a ground line that is at ground potential. 27 and 28 are wirings made of a second aluminum layer formed through an insulating layer 29, and 27 is a wiring line between the gate electrodes 8 and 9 parallel to them and crossing the signal lines 19 and 20. A connection that electrically connects the signal lines 18 and 21, with one end connected to the end of the signal line 18 through the through hole 30 and the other end connected to the end of the signal line 21 through the through hole 31. line, 28 is the gate electrode 15,1
6, parallel to them and intersecting with the signal line 23, one end is connected to the end of the signal line 22 via the through hole 32, and the other end is connected to the end of the signal line 24 via the through hole 33. is connected to the signal line 22
34 is an oxide film which is an insulating layer, and 35 is a substrate.

However, in this way, the signal lines 18 and 21 of the first aluminum layer or the signal lines 22 and 24 are connected to each other by the connecting wire 27 or the connecting wire 28 of the second aluminum layer. In this case, the connection lines 27 and 28 are
5 and 16, the second aluminum layer cannot be used for other signals at this point because it gets in the way, and is extremely restricted in connection with the internal circuit 3. It was something I would receive.

On the other hand, in order to make effective use of the second aluminum layer for signals, it is conceivable to use a device as shown in FIGS. 4 and 5, for example.

In Figures 4 and 5, 36 and 36 are gates 1
5 and an n-type impurity diffusion region 14, which is an active region on both sides of the gate electrode 16; An oxide film consisting of an insulating layer that separates the MOS transistor including MOS transistor 13b from a logic functional element as one component.
It is formed on one main surface of the substrate between 6 and 6.
Reference numeral 37 denotes a P-type or N-type impurity diffusion region formed on one main surface of the substrate 35 separated from the logic functional element by the oxide film 36 at a position passing through the signal line 23 which will be formed later, and covering this upper surface. The signal line 2 is connected through the through holes 38 and 39 that penetrate the oxide film 26.
2 and the end of the signal line 24, respectively, to connect the signal lines 22 and 24.

In this way, the electrical connection of the signal lines 22 and 24 formed in the first aluminum layer is made in the impurity diffusion region 37 of the wiring region formed on the substrate by oxide film separation. Although there is an advantage that the second aluminum layer in the wiring area can be used for signal lines, there are problems in manufacturing because the wiring area cannot be placed anywhere and must be specified.
In particular, it was unsuitable for forming a master slice type gate array.

This invention has been made in view of the above-mentioned points. Gate electrodes are arranged in parallel on one main surface of a semiconductor layer, and active regions are formed in the semiconductor layer between each gate electrode, so that a plurality of MOS transistors are formed. In a semiconductor integrated circuit device, multiple
At least two logic functional elements are configured using the required number of MOS transistors, and at least two MOS transistors are positioned between these logic functional elements, and these gate electrodes are held at a predetermined potential at which the MOS transistors are cut off. This is done in the separation area between the logic functional elements, and these two
The active region formed between the gate electrodes of two MOS transistors is used as a wiring region for signal lines, eliminating the need for a metal layer for connecting signal lines, and making it possible to effectively use this area as a signal line. , the purpose of this is to enable the wiring area of signal lines to be arbitrarily selected.

An embodiment of this invention is shown below in Figures 6 and 7.
To explain based on the diagram, in the diagram 8, 9, 4
0, 41 are P-type diffusion regions 4, 5a, 42, 5b,
gate regions 10, 43, 44, formed between 6 and 6;
With gate electrodes formed in parallel on 11, a P-type impurity diffusion region and a gate region each serving as an active region constitute a P-channel MOS transistor. 15, 45, 46, 16 are n-type diffusion regions 1
The gate electrodes are formed in parallel on the gate regions formed between 2, 13a, 47, 13b, and 14, and the n-channel MOS transistor is formed by the n-type diffusion region and the gate region, each of which becomes an active region. , and the opposing P-channel MOS transistor form a pair to form complementary MOS transistors. Note that the gate electrode 8 and the P-type impurity diffusion regions 4 and 5a which become active regions
A P-channel MOS transistor consisting of a gate electrode 15 and an n-channel MOS transistor consisting of an n-type impurity diffusion region 12 and 13a serving as an active region.
The complementary MOS transistor paired with the MOS transistor may constitute a logical functional element by itself, or may be combined with one or more complementary MOS transistors (not shown) arranged on the left in FIG. A P channel is composed of a gate electrode 9 and P-type impurity diffusion regions 5b and 6 which serve as active regions.
A complementary MOS transistor, which is a pair of a MOS transistor and an n-channel MOS transistor constituted by a gate electrode 16 and an n-type impurity diffusion region 13b and 14 serving as an active region, constitutes a logical functional element by itself, or One or more complementary MOSs arranged on the right in Figure 6
It constitutes one logical functional element in combination with a transistor (not shown). 48,4
9 is formed through the insulating layer, and a gate electrode 40
and the end of the gate electrode 41 and the positive power supply line 1
By supplying positive power to the gate electrodes 40 and 41 through contact holes that electrically connect the gate electrodes 40 and 7,
Channel MOS transistor and gate electrode 4
1 to electrically isolate the P-type impurity diffusion region 42 between the gate electrodes 40 and 41,
The gate electrode 43, the P-type impurity diffusion region 42, and the gate region 44 form a separation region between logical functional elements, and a P-channel MOS transistor constituted by the gate electrode 40 and a P-channel MOS transistor constituted by the gate electrode 41 are formed. The MOS transistor constitutes a separation element. 50,51
are contact holes formed through the insulating layer and electrically connect the ends of the gate electrode 45 and the gate electrode 46 to the ground wire 25 serving as the negative electrode power supply, respectively.
By making it a negative potential (generally ground potential),
An n-channel MOS transistor consisting of a gate electrode 45 and an n-channel MOS transistor consisting of a gate electrode 46
This is to electrically isolate the n-type impurity diffusion region 47 between the gate electrodes 45 and 46 by making the channel MOS transistor non-conductive, and the gate region corresponding to the gate electrode 45, the n-type impurity diffusion region 47,
and a gate region corresponding to the gate electrode 46 form a separation region between logic functional elements. It constitutes. 52 is formed penetrating the insulating layer 26 and connects the end of the signal line 18 and the P-type impurity diffusion region 4.
A contact hole 53 electrically connects 2 with
is a contact hole that is formed penetrating the insulating layer 26 and electrically connects the end of the signal line 21 and the P-type impurity diffusion region 42;
2, the signal line 18 and the signal line 21 are electrically connected to the P-type impurity diffusion region 42 by passing through the signal lines 19 and 20 using the impurity diffusion region 42 as a wiring region. It is connected to the 54 is formed penetrating the insulating layer and connects the end of the signal line 22 and the n-type impurity region 47.
A contact hole 55 is formed through the insulating layer to electrically connect the end of the signal line 24 and the n-type impurity region 47. In order to electrically connect the line 22 and the signal line 24 to the n-type impurity diffusion region 47, the impurity diffusion region 4
The signal line 22 and the signal line 24 are electrically connected to each other by passing through the signal line 23 using 7 as a wiring area.

With this configuration, even on the wiring area between the signal line 18 and the signal line 21 and on the wiring area between the signal line 22 and the signal line 24, the signal lines 18 to
The second aluminum layer formed on 24 can be effectively used as another signal line, and complementary type MOS transistors can be placed at desired positions among multiple pairs of complementary type MOS transistors.
MOS transistors can be used to provide isolation regions for logical functional elements and wiring regions for signal lines.

In the above embodiment, the p-type impurity diffusion region 42 and the n-type impurity diffusion region 47 are used as wiring regions.
Although each of these is used, either one may be used, or the same effect can be obtained by connecting the P-type impurity diffusion region 42 and the N-type impurity diffusion region 47 in series.

Further, in the above embodiment, the signal line has two aluminum layers, and the signal line formed of the first aluminum layer is also an impurity diffusion layer. Although the connection is made in the wiring area, the signal line formed on the second aluminum layer may also be connected, and even if the signal line has three or more aluminum layers, the aluminum layer on either layer may be connected. A similar effect can be obtained even if signal lines formed in layers are connected using impurity diffusion regions. Further, in the above embodiment, an aluminum layer was used as the wiring material for the signal line, but a metal layer other than the aluminum layer may be used as necessary.

As described above, in this invention, gate electrodes are arranged in parallel on one main surface of a semiconductor layer, and
In a semiconductor integrated circuit in which an active region is formed in a semiconductor layer between each gate electrode and a plurality of MOS transistors are configured, a logic functional element is configured using a required number of a plurality of MOS transistors, and at least two MOS transistors are placed in the
The MOS transistor is held at a predetermined potential that is quickly turned off and used as a separation region between logic functional elements, and the impurity diffusion region formed between the gate electrodes of these two MOS transistors is used as a wiring region for a signal line. This eliminates the need for a metal layer for connecting signal lines, and this part can be effectively used as other signal lines, making it easy to arrange and route wiring on the gate electrode. Since this can be achieved by selecting two of a plurality of MOS transistors arranged in parallel, it also has the effect of increasing design margin.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of a gate array, Fig. 2 is a top view showing the internal circuit of a conventional gate array, Fig. 3 is a cross-sectional view of Fig. 2, and Fig. 4 is an internal view of another conventional gate array. 5 is a sectional view of the main part of FIG. 4, FIG. 6 is a surface view of the main part showing the internal circuit of a gate array according to an embodiment of the present invention, and FIG. 7 is a surface view of the main part showing the circuit. FIG. 6 is a sectional view taken along line - in FIG. 6; In the figure, 4, 5a, 42, 5b, 6 are P-type impurity diffusion regions, 8, 9, 40, 41 are gate electrodes, 12, 13a, 47, 13b, 14 are N-type impurity diffusion regions, 15, 16, 45 and 46 are gate electrodes, 17 is a positive power supply line, 18 to 24 are signal lines, 2
5 is a ground wire, 48 to 51 are contact holes,
52 to 55 are contact holes. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A plurality of MOS transistors in which a plurality of gate electrodes are arranged in parallel on one main surface of a semiconductor layer and an active region is formed in the semiconductor layer between each gate electrode. , multiple MOSs above
It is composed of at least two logic functional elements constructed using the required number of transistors, and at least two MOS transistors located between these logic functional elements, and the gate electrode of the MOS transistor is connected to a predetermined gate electrode that turns off the MOS transistor. A configuration in which the semiconductor region under the two gate electrodes and the active region existing between the semiconductor regions are held at a potential and serve as isolation elements, and the active region serves as a wiring region. A semiconductor integrated circuit device characterized by: 2. The semiconductor integrated circuit device according to claim 1, wherein the MOS transistors are complementary MOS transistors that are a pair of a P-channel MOS transistor and an N-channel MOS transistor.