JPH01228020A - Comparing device - Google Patents

Abstract

PURPOSE:To attain arithmetic processing speed at high speed by eliminating the subtraction of mutual operands only when the size of a pair of operands can be decided from the number of the effective digits of a pair of the operands. CONSTITUTION:When an operand 1 is stored into a register file 111 and an operand 2 is stored into a register file 112, the number of effective digits is set to registers 104 and 105, compared with mutual registers and the sizes of operands 1 and 2 are compared. In this case, for the larger number of the effective digits, the operand also becomes large. Only when the number of the effective digits is equal, so that the size of the operands 1 and 2 is decided, registers 111 and 112 are subtracted. When the number of the effective digits of the operands 1 and 2 is different and subtraction is not executed by the comparing processing, since the size of the operands 1 and 2 can be discriminated, the processing can be speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a comparison device that compares and determines the magnitude of the absolute values of a pair of operands in a main storage device.

(Prior Art) When comparing the absolute values of the decimal numbers of operand 1 and operand 2 in the main memory, conventionally, as shown in FIG.
Operand 1 and operand 2 are subtracted (step 531), and the resulting information (presence or absence of borrow, whether the subtraction result is zero or not) is used to determine the magnitude of operand 1 and operand 2 (step 531). 532).

(Problem to be Solved by the Invention) Therefore, in the past, when comparing the absolute values of the decimal numbers of operand 1 and operand 2, it was necessary to always perform subtraction processing between operand 1 and operand 2, which resulted in a reduction in processing speed and This led to an increase in traffic congestion.

In the present invention, when comparing the absolute values of operand 1 and operand 2, the priority calculation circuit is effectively used to omit subtraction when the magnitude can be determined without subtracting operand 1 and operand 2. The purpose of the present invention is to provide a comparison device that speeds up processing.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a means for calculating the number of significant digits of a pair of operands read from a main storage device, and a means for calculating the number of significant digits of each operand calculated by the means. A pair of registers for storing the number of digits, a comparator that compares the contents of the registers and determines whether they are large or small and match, and a flip-flop that stores the results of the judgment of size and match obtained by the comparator. , means for determining the magnitude of the absolute value of the pair of operands read from the main memory based on the contents of the flip-flop, and it is possible to determine the magnitude of the pair of operands from the number of significant digits of the pair of operands. The structure is such that subtraction between operands is omitted only in such cases, thereby increasing the speed of arithmetic processing.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the apparatus according to the present invention.

In the figure, 100 is the main storage device, 101 is the main storage device 10
Read the operand in 0 and write the register file ill
, +12.

Reference numeral 102 indicates read data (
RD) or the output data (SD) of the subtracter 113.

Reference numeral 103 denotes a priority calculation circuit that calculates the priority (number of significant digits) of an operand when storing the operand in the main storage device 100 into the register files 111 and 112.

104 is a register (RPU) for storing the priority of the operand stored in the register file (RU) 111 with the priority obtained by the priority calculation circuit 103; 105 is the priority calculation circuit 103;
Register file (RV) with the priority obtained in
This register (RPV) is used to store the priority of the operand stored in the register 112.

10B is a register (RPU) 104 and a register (RPV
) 105.

107 stores the comparison result of the comparator 10B, and registers (
It is a flip-flop which becomes 1' when RPU) 104 is larger than the register (RPV) 105, and becomes "O" otherwise.

108 stores the result of the comparator 10B and registers (RP
It is a flip-flop that becomes 0' when U) 104 and register (RPV) 105 are equal, and 0' otherwise.

109 is a register (RUCNT) that specifies the address of the register file (RU) 111, and 110 is a register (RVCNT) that specifies the address of the register file (RV) 112.

111 is a register file (RV) for storing operand 1 in main memory 1[1[1].

A subtracter 113 inputs the register file (RU) 111 and the register file (RV) 112.

114 is a flip-flop (F B) that stores the borrow of the subtracter 113; 115 is a flip-flop that examines the output from the subtracter 113 and subtracts operand 1 and operand 2 in the register file (RU) 111 and register file (RV) 112; This is a zero detection circuit that detects whether the result is zero. A flip-flop 11B holds the output of the zero detection circuit 115, and becomes "1" when the subtraction result of the subtracter 113 is zero, and becomes "0" otherwise.

FIG. 2 is a flowchart 1. showing a comparison routine of the embodiment 1.

An embodiment of the present invention will now be described with reference to FIGS. 1 and 2.

First, operand 1 is stored in the register file (RU).
and store operand 2 in register file (RV) 1.
12, each priority (
number of significant digits) in register (RPU) 104 and register (
RPV) 105, and cor register (RPV) 105.
U) 104 and the register (RP V) 105 to determine the magnitude of operand 1 and operand 2 (steps 521-825 in FIG. 2).

In this case, the larger the priority (number of significant digits), the larger the operand. And the priority (
The register file (R
U) Subtract ill and register file (RV) 112.

The register file (RU) ill at this time.

(RV) 112 subtraction processing and the same register file (
RU) 111, (RV) 112 (f) The storage process of the OHERA> code is the same as the conventional one, and its explanation will be omitted here.

By comparing the absolute values of operand 1 and operand 2 through the comparison process of the embodiment described above, operand 1
If the priority (number of effective digits) of operand 1 and operand 2 are different, the magnitude of operand 1 and operand 2 can be determined without subtraction, so that processing speed can be increased.

[Effects of the Invention] As detailed above, according to the comparison device of the present invention, there is a means for calculating the number of significant digits of a pair of operands read from the main storage device, and a means for calculating the number of significant digits of each operand calculated by the means. A pair of registers for storing numbers, a comparator that compares the contents of the registers and determines the magnitude and equality, and a flip-flop that stores the magnitude and equality obtained by the comparator. A case where it is possible to determine the magnitude of a pair of operands based on the number of significant digits of the pair of operands, with means for determining the magnitude of the absolute value of the pair of operands read from the main memory based on the contents of the flip-flop. By adopting a configuration in which subtraction between operands is omitted only in this case, the calculation processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG.
The figure is a flowchart showing the comparison processing routine of the above embodiment, and FIG. 3 is a flowchart showing the conventional comparison processing procedure. 100... Main storage device, 101... Shifter, 102
...Selector, 103...Priority calculation circuit, 104...Register (RPU), 105...Register (RPV), ioe...Comparator, 107...
Flip-flop (FUGV), 10B...Flip-flop (FUEV), 109 L/JIS 9 (RUC
NT), 110...Register (RVCNT), lll
...Register file (RU), 112...Register file (RV), 113...Subtractor, 114...
- Flip-flop (FB), 115...Zero detection circuit, llB...Flip-flop (FZ). Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] A means for calculating the number of significant digits of a pair of operands read from the main storage device, a pair of registers for storing the number of significant digits of each operand calculated by the means, and comparing the contents of the registers with each other, A comparator that determines size and match, a flip-flop that stores the size and match judgment results obtained by the comparator, and a pair of operands read from the main memory based on the contents of the flip-flop. 1. A comparison device comprising means for determining the magnitude of a value.