JPH01231585A - Address code mixing device - Google Patents

Abstract

PURPOSE:To realize the transformation of an address code mixing device into an IC and to prevent the illegal use of the charged broadcast service by realizing the digital processing for formation of a total digital circuit. CONSTITUTION:A horizontal period of a prescribed field of the TV signal into which each bit of an address code is mixed is selected at pseudo random via an initialization processing means 7 and a PN code generating means 8. Then each bit of the address code can be put into a front pouch of the selected horizontal period in a digital form. As a result, the address code allocated to a terminal receiving device is always mixed into the TV signal outputted from said terminal receiving device. Thus a terminal equipment can be detected quickly, surely and easily in case an illegal copying action is performed via said terminal equipment. In such a way, the illegal use is prevented for the charged broadcast service and an address code mixing device is easily transformed into an LSI via the total digitalization.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address code mixing device in a receiving device, and in particular, to an address code mixing device in a receiving device, and in particular, to an address code mixing device for a receiving device for a terminal for paid information such as right-handed broadcasting. Address code II that contributes to preventing ? Regarding the input device.

``Prior Art'' Currently, information provision services are being provided using convenient communication systems, such as paid broadcasting such as CA-TV, and other information provision using personal computer communications. In these communication systems, only members who have paid a predetermined fee are provided with a terminal receiving device unique to the communication system that allows information to be provided, so that information is not available to anyone other than the member. ing.

However, in the above case, it may actually happen that the members use the reconstructed stomach to provide the information obtained by legitimate members on a3 to a third party, and such situations of unauthorized use may occur. It is clear that leaving the situation unaddressed will result in a huge loss for pay TV operators.

Therefore, in the past, double yen! J Prohibition: Preventing the duplication of 41 format information by inserting a code into the information data or including a screen in the video signal that displays the unique address number assigned to the terminal] J trying to get 1, sea urchin I [.

However, the conventional copy protection 11 described above is generally technically simple! 44 can be removed,
11. In other words, it's something you can easily get."
S: 1-) If you use a snow device, you can relatively easily remove the screen containing the double VJ 11 Niko Doi S number and the address number of the terminal.

Therefore, in order to solve the above problems, the applicant [3]
In L1 Patent Application No. 62-238763, we proposed a method for adding addresses and inserting notes. According to this address code mixing device, address information unique to the terminal device that received the signal is mixed into the video signal, and furthermore, this address information cannot be easily separated from the No. 60 signal. When an unauthorized copy is made, the terminal device that made the copy can be quickly and easily discovered, thereby preventing unauthorized copying. By the way, the above address code mixing device generates an oscillation signal of a predetermined frequency and performs frequency modulation on this signal to obtain address information, so filter processing is required and the overall problem is It was constructed using analog technology. However, in line with the demands for more integrated circuits and smaller devices, digitalization of circuits is also strongly desired.1.The purpose of the present invention is to enable digital processing and to convert the entire circuit into a digital circuit. By providing a configured address-code straddle, the device can be integrated into an IC,
The aim is to effectively stop the use of I+1 broadcasting and novice services.

[Means to Solve the Problem] The address code mixing device () in the terminal receiving device that can receive the pay broadcasting service according to the present invention uses the address code on the right assigned to the terminal receiving device. an initialization processing means for generating an initial value in response to a synchronization signal of the Brevisini signal; a PN number generation means for generating a 1]N code based on the initial value; Based on this PN code, the storage means is accessed, and each address code is incremented by +111 in the horizontal period of the television signal, and the address code is previsited. 51:j is composed of address code combination means and l) t t.

According to the above-mentioned address code mixing device, the initialization processing means and the [ ] A period is pseudo-randomly selected and thus addresses the front porch of the selected horizontal period'−
The address code assigned to the terminal receiver 4M'6 WI is always included in the television signal output from the terminal receiver. .

[Examples] Preferred embodiments of the present invention are shown below in attached 4 drawings.]
-Follow-C Explain.

FIG. 1 shows a terminal receiving device including an address code mixing device according to the present invention, and this terminal receiving device is a receiving device for a terminal device that receives a right r1 broadcast signal. 1st
In the figure, 1 is an address code mixing device according to the present invention, 2 is a TV tuner, 3 is a descrambler for restoring scrambled television signals used in CATVW, 4 is a video signal amplification circuit, and 5 is a video signal amplification circuit. is the video signal output terminal f. The address code mixing device 1 and the descrambler 3 are arranged as shown in block 100.
It is physically sealed and integrated so that it is difficult to open. This can be accomplished by incorporating them into the same package or forming them on the same chip.

In the above configuration, the video and B audio signals, that is, the television signals scrambled and sent out on the transmitting side, are received by the TV tuner 2, and then sent to the descrambler 3.
and address” - is provided to the iIP person device 1. The descrambler 3 cancels the suffragne pull, takes out the normal 4j video and the high 7B A, and outputs it. 5.Address that is human-powered
- The code entry device 1° C. is assigned to the relevant end block 16 based on Synchronization No. This video signal is sent to the video signal amplification circuit 4. Therefore, if this composition is J, the video signal amplification circuit 4 has an address in the composite video 111 supplied to the video signal amplification circuit 4.
This means that the address code prepared in the personal information card 1 is definitely mixed in. The television signal output from the output terminal r5 is then displayed as OR]-.
- Used for recording by R etc.

Next, a detailed configuration of the address code mixing device 1 and a method for adding an address code to a video signal will be explained.

First, we will explain the unique address code assigned to the terminal device and the location and manner in which it is mixed. Considering the actual operational aspects, the number of address codes should be changed to 64 bits 1.5, 4 f.In other words, considering the current social situation and industry W situation, ■Manufacturer classification, ■Equipment Types of, ■terminal devices! 11 The numbers of pimils that must be sold in order not to contain any artificial or artificial ingredients are 20 bits (approximately 1,000,000 nets per minute), 10 pis I (approximately 1,000 types), and 34 bits (approximately 160 Therefore, it is sufficient to allocate 100 million units), so at least the address code C for 64 pins is sufficient.
It is enough. Also, the address code is 64 bits 1~O''
Or, the insertion position at a3 of the pulse corresponding to "1" in the video signal is given by PA1''', as shown in FIG. In the nth horizontal period, scanning period 1 ~
t200 (for example, the position of the right edge t of the screen) or during the retrace period. 2 iio
io.

(for example, the position from Freon 1 to Board t1o1). In the following embodiment, a case will be described in which the signal is inserted at the tlol position during the retrace period. Regarding the J3 address code, correspond to II 1 II, for example, insert a narrow pulse with a pulse width of 0.3 μs in the 101st place 1d, and for "O", insert nothing for -C and take it as true. .

As mentioned above, if you send the address code for 1 to the terminal from 64 bits to 1, the address code will be mixed in! All you have to do is cover the horizontal period of the video signal by specifying 64 points.
These specified locations are fixed and continuously addressed.
If each address in the code is traced by mixing in the addresses, there is a risk that an unauthorized user will easily discover the address in which C is mixed in. Therefore, address code mixing device 1 according to the present invention
Now, as will be described later, 64 horizontal periods in which each bit is inserted without forming an address code are pseudo-randomly changed. In other words, the address ``do mixed-person visit 1'' is, for example, 2
8-1 (255) Accomplished P N '+3 (Psudo-noise code) of m series of P1~
The 255-bit P N
The first 64 1'' portions of number N correspond to the horizontal period, and among the 64 horizontal periods corresponding to ``1'', correspond to ``1'' in address codes a1 to a64. -9
= Determine the circuit configuration to mix the above-mentioned pulse into the corresponding horizontal period.

Next, the construction of the address code mixing device 1 will be explained with reference to FIG. Reference numeral 6 denotes a synchronization signal dividing circuit, which extracts various necessary signals from the composite video signal supplied from the TV tuner 2, such as horizontal Jij 1st period signal (hereinafter referred to as H pulse), vertical synchronization signal (hereinafter referred to as V pulse), and horizontal blanking M y. Separate the timing signal and override the output. Reference numeral 7 denotes an initialization processing circuit, which inputs the V pulse from the synchronous signal branch 1 circuit 6 and sets an initial value for each field in synchronization with this. This initial value consists of 8 bits, going from 00000001 to 111
The initial value of 1°, from which any value is selected from 255 numerical values of 11111, will be represented by d to d8 below. 8 is a PNN code generation circuit, and initialization (1++ d ”□
ds and synchronization signal separation circuits 6 to 1.
A pulse is input, and as described above, 255 8-bit pattern signals are generated in synchronization with the L1 pulse, thereby creating and outputting a P N code for 255 bits 1.

1 Here, an example of a known PN code generation circuit 8 will be briefly described based on FIGS. 2 and 3. As shown in Figure 2,
PNMN code generation circuit 8F1-Register 80 and 3+
It is composed of Jl other side OR gates t-81, 82, 83, etc. The shift register 80 has 2 to 27 (1) 8 hits
-Minute right L/, +jt On the other side OR K-1-81 is 23
and 27 bit outputs are input, υ1 transitive OR gate 8
In 2, the human outputs of 21 and 22 are human power, exclusive OR
'y' -1-83 Ni4J +Jl other side R goo 1~
Each output of 81 and 82 is input, and the 1-no alternative OR game 1
The output of ~83 is connected to feed back to the input power 9i of the dinomyl register 8o, in such a configuration,
Initial value d - d8 of 8 pins 1- from initialization processing circuit 7
is loaded into the shift register 80, and the synchronization signal separation circuit 6
If we clock it 255 times with the 1'' pulse given by
255 as the 27 bit output of Gino 1 to register 8o
P N 'FJ' @ to Pitsu 1 can be obtained.

Now, as shown in Figures 2 and 3, the initial count is 101110.
01, the state of the 8 bits in the shift register 80 is as shown in FIG. As a result, shift register 8 in FIG.
A bit string shown in a column with respect to the pins 1 to 2' of 0 is generated at the output terminal of the shift register 80 (the pins 1 to 27). .

When the 256th clock is run, the internal states of shift 1 to register 80 return to their initial states. Regarding the Gino Mill resistor 80, its manual type may be either a parallel type or a serial type, but its output type must be a parallel type.

Returning again to FIG. 1, the explanation of the configuration will be continued. 9 is a mixed gate forming circuit. The mixed gate forming circuit 9 receives the V pulse from the synchronizing signal separation circuit 6, the initial value from the initialization processing circuit 7, and the PN code from the PNN code generation circuit 8. As shown, the PNF signal (see Figure 6) synchronized with the horizontal period of the television signal.
) is the pulse signal φ13 (Fig. 6 (c))
This pulse signal φ1 is applied from the N code generation circuit 8 to the mixing gate forming circuit 9 in the 13 mixing gates 1 to 9.
It includes a circuit section that generates a pulse signal φ12 in response to a change in the state of °C1 based on 3, and generates goo 1 to pulse φ14 in response to a rising from 'O' to '1'. The gate pulse φ14 is a pulse signal for superimposing each bit of the address 1 on (1o1) during the horizontal period of the composite video signal in response to "1" of the PN code. The mixing goo 1 ~ formation circuit that covers the above functions 4:i can be realized with one 3-man AND gate, for example, and can be easily made of bamboo by a digital circuit engineer, so we will explain the specific configuration. is omitted.

Gate pulse φ1 output from mixed gate forming circuit 9
4 is supplied to an address signal generation circuit 10 and an address code mixing circuit 11.

The address signal generation circuit 10 is constituted by an address counter, and manually generates a V pulse from the synchronization signal separation circuit 6 at the edge of the gate pulse φ14. This address signal generating circuit 10 counts gate pulses φ14 with a counter for each field, and generates an address signal in synchronization with the horizontal period of the alignment signal. This address signal is supplied to a circuit 11 containing address status -'1 to 3-.

The specific configuration of the address code mixing circuit 11 is shown in FIG. , an OR gate 13 that inputs the output of the address ROM 12 to one input terminal, a pulse generator 14 that receives the output of the OR gate 13 and generates a pulse with a pulse width of 0.3 μs, and has three input terminals. It consists of a switching gate 15 that makes the output of the pulse generator 14 different from the output of the pulse generator 14 at one input terminal. The other two input terminals of the switching gate 15 are supplied with the composite video signal φ11 from the descrambler 3 and the gate pulse φ and pulse signal φ12 from the mixing gate forming circuit 9. The output terminals of the switching groups 1 to 15 are connected to the input terminal of the video signal amplification circuit 4 as the output terminals of the address code mixing circuit 11. This switching signal I.15 is a composite video signal φ11.
1 to 1, which passes through the output without distortion, and includes a clamp circuit, etc., for matching the levels of the output of the descrambler 3 and the output of the pulse generator 14, and
The initial value d.-d8 output from the initialization processing circuit 7 is input to the other input terminal of the OR gate 1-13. 1
Next, we will explain how the address code is mixed in due to the manual structure. As described above, each bit 1 to fl1 of the 64-bit address code is applied to the frame pouch of an appropriately selected horizontal period of the composite video signal φ11. FIG. 7 shows a part of the television control signal (same as the j6J combined video signal φ11) in units of fields. In Figure 7, y, yo, yo41゜y,..., Vi
,,□1. V,! , V□1. Each n+2 represents one field. In this example, there is one field y. ,,2. y□1. . . . The address code a-a64 is inserted. J3 In this case, F. 4
．． The signal φ16n shown in FIG. 8 is mixed into the two previous field y, y of 2 jj+, l+, . . . , and the previous field y. 41. yl.

... into which the signal φ17 shown in FIG. 9 is mixed,
The signal φ is a sequence of 16 falling in the field y, y□1.
In the 11 horizontal periods n-・n1o-C1 start bit "'
Insert ``10'' and ``10'' and n
This is an 8-bit signal with consecutive '0's from n9 to n9. This signal φ16 is used to detect address codes a to a64, and it is used to detect that an address code exists after this signal φ16. This is a start signal for notifying the field V, V,
! Continuation 17 n
11 horizontal periods k +1. At 1o in ~, start pi [~” 10 “dosu [~tsubu pi 1~]” 1
0'' and set the initial value d from k to 9 as described above.
This is a signal in which signals 1 to d8 are mixed. This signal φ17
is also used for address code detection and is a set signal for setting the shift register on the detection side.

The signal φ16. φ1. Like the address code, each bit of is inserted into )[=1 tot t1o1 of each horizontal retrace period.

Address n+2 mixed into fields y and y
j! +1 Scode a~”64 is 0 mixed in roughly the first half of each field in this example, and here, the 255 mentioned above
The correspondence relationship between horizontal scanning line numbers such as PN code of bit series and address codes a- and a64 will be explained according to FIG. 10.
1 to indicate the number, PN code, and address code, respectively, of the PN code. In this example, the 18th ('' corresponds to the 1st bit of the PNfm code, and the 272H (that is, the meaning of 91-1 in the next field) corresponds to the 255th bit. However, the horizontal scanning line number and l) N code How to respond to C is optional.
be. Also, if the number of bits of the PN code is less than the number of horizontal scanning lines in one field, there will be no problem1.
If each bit a""a64 of the address code to 64 pits 1 is made to correspond to '1" of PN↑9 shown in FIG. 10, the p[- number in the figure will be around 128H.

'O''' in PN code, 11111 minutes
, and are almost equal, so in my notebook, the number sequence 1/255 becomes medium heat, and therefore it becomes around k -1 - 176145H. In this way, when transmitting a 64-bit address code, it is necessary to add 2 bits corresponding to one field.
72 N will not be used completely, in fact a3 J
: A half is enough. In Figure 10, 181-1.2
111.221-1. ...and P N The address code a corresponds to the horizontal scanning line where the pitches 1 to 1 in the right column are 1''.
, a , a , . . . pulses for each bit are inserted. The m-series PN code synchronized with the horizontal scanning line is generated by clocking the shift register J3 in the shift register 80 in FIG. After counting 64 times, the clock is stopped, and the horizontal scanning lines from (k + 17) 11[1 to 272H are ignored and covered.

The scrambled composite video signal received by TV duplex 2 is descrambled by descrambler 3,
The signal is supplied to the switching gate 15 of the address code mixing circuit 11 as a normal composite video signal φ11. The 1-1 pulse and the V pulse are outputted from the synchronization signal dividing circuit 6, and the initialization processing circuit 7 sends the initial value d8 to the OR gate 13 of the address code mixing circuit 11 and the PN code generation circuit 8.

, the PN code generation circuit 8 generates a PNN signal using the initial values d1 to d8 and the 1-1 pulse -IF3- clock, and aA combination -1 to d8.
A gate pulse φ14 is generated to the corresponding part i[Tl. The generation position of the 1-go 1 pulse corresponds to the Freon 1 hebage of the composite image 48 months. This gate pulse φ14
are supplied to the switching circuits 1 to 15 of the address code 8 to the combining circuit 11 and the address signal light 1 to the circuit 10.

In addition, the switching gear 1-15 is shown in Figure 4.
diL/tai1 and bow φ12 are supplied on the same line,
.

In the address code mixing circuit 11, the switching gate 15 has d
3-1 C1 composite video signal φ11 (TV Series No. 8)
As shown in FIG. 7, signals φ16,
φ17, a64 is mixed into the address code a1. Regarding the fields y and y□1, [1] The initialization processing circuit 7 outputs the open signal φ16 (FIG. 8) for the horizontal period nf) to n10, and the signal φ12 is output from the matching circuit 1 to the formation circuit 9. and then OR goo 1-1
3, is applied to the switching gate 15 via the pulse generator 14. Then, because they are synchronized with each other and the fields yn and V1- of the combined video signal φ11 are
The signal φ16 is mixed into the front 1 to the porch in the horizontal period no' to n10. field y. , 1.

For yl, Jarji < dt keg-1~formation horizontal period k. - During klo, output φ12, and generate the initial value d and d8 from the initialization processing circuit 7 through OR groups I to 13 and the pulse generator 14, and give these to switching groups i to 15. 1, whereby the field y. of the composite video signal φ11. ,1.

Horizontal period k of y. Signal φ on the front porch of 1o in ~
Mix and cover 1□ (Figure 9).

Next, the address of field y, y□1]-n+2 will be explained. , address signal generating circuit 10 generates an address signal in response to gate pulse φ14 applied from coupling gate forming circuit 9, and supplies this address signal to address ROM 12. Address signal generation circuit 10
Specifically, for example, is a binary counter to 6 bits 1,
Specify the address inside the address ROM 12 using 6 bits. The address signal generation circuit 10 clears each field with a V pulse, and pulses ψ1 to ψ14 are cleared by pulses 1 to ψ14.
For example, in field y, 18]' (
From the position of the FF signal φ12n→2, the address signal +3 is generated in synchronization with each gate pulse while running this goo 1 ~ pulse 1 ~ according to the gate pulse φ14 depending on the presence or absence of II II II of the P N code. Circuit 10 is 0 0 0 0 0 0 h
Soro sequential 1 1 1 1: Outputs the address signal at J:, 1 address ROM 12 ooooo
Since o corresponds to al, 111H1 corresponds to "64," and the interval corresponds to a2 to a63, respectively, υ, the address signal generation circuit 10 synchronizes the stored contents with the gate pulse φ14.
Accordingly, the reading of the address ROM 12 changes depending on the output horn of the m-series P N code '1' water Xp light period. When the output of the address ROM 12 is '1', the OR ~13, a predetermined high level signal is given to switching groups 1 to 15 via the pulse generator 14, (before)
A 0.3 μs pulse is inserted into the front pouch t like a book. In this way, fields y, yn i2
1 (of 64 pseudo-randomly selected horizontal periods of 1) [J
Address codes 81- and a64 are mixed into each of the toji pouches. Note that the contents of address codes a1 to a64 are 0.
'', there is no pulse.

Also, a field y.includes an address. +2.

Vl. , 1. Regarding the operation of the address ROM 12 with d3+ in other fields, the dimensions J are shown in FIG.
: The output inhibit signal φ18 is supplied from the initialization processing circuit 7 to the output control (read inhibit or deep enable) terminal f of the address ROM 12.

It is clear that the address codes a1 to a64 are mixed into the other fields due to this formation. be done.

As mentioned above, the address code mixing circuit 11 switching group 1
~15, the fin n+2 of the composite video signal φ11
1+1. 64 water cut-off period front porches t1 selected in [J pseudo-random mold y, y]
Each bit 1 to 1 of the address code is mixed into 01, and then the video signal is supplied to the video signal amplification circuit 4. Therefore, the predetermined field of the video signal output from the video signal amplification circuit 4 always contains the address code stored in the address ROM 12 and assigned to the terminal in question.

On the other hand, V T-F < +2 from the video signal recorded by the customer.
When detecting the address code, first detect and override the start signal φ, 6 at node (y), and then detect the arrival of the field containing the address code a 64. 'F IIJ and capture initial lli'ld ~d8 in field y,
Detection device +1 1 Initialize the shift register prepared at the neck and input the next field y0, 2 by -(Shift the shift register by 11-1 from 181-1 to make the PN number appear as CI, and of the retrace period of video No. 18 corresponding to '1'']
Detect the address code from 1 controller 1 to port t1o1. Note that regarding the m-series PN code, in the case of 28-1, there will not be eight consecutive "o"s, so detect the field y. Lost sword, PN of field yn+2
It is impossible to mistake a part of the code for a star 1 to signal.

In the above description, the pulse width of the pulse mixed into the neck of the front porch t101 was set to 0.3 μs,
Since the fundamental frequency component of this pulse can be approximately 3.3/2 HIIz, even if it is recorded on a VTR, this fundamental frequency component will not be lost.

As mentioned above, the following modifications can be made in the embodiments of the present invention. First, field y. , omit 1,
It is also possible to transmit the contents of field yn+2 after field yn.

Lee then inserts the initial 8 pits (i"' d 1 to d8) into the front 1-porch of the horizontal period that corresponds to the first 8 '1's of the PN code, and then
If a 64-bit address code is used as described above to correspond to 1 II, the number of fields can be reduced by one field. Also, the interval between the field where the start signal φ16 is inserted and the field where the address code is inserted is arbitrary1.Additionally, the start signal φ16 added to FIGS. 8 and 9, and the cell 1 to signal φ are inserted.
Horizontal cutting Ffil no to n1o.

The position of 1o between k and ~ is also arbitrary.

〇−24= [Effect of the invention] As is clear from the explanation of the twins, the present invention J, if J3 is in a predetermined field of a television signal, and C is a right-handed broadcasting terminal in a pseudo-randomly selected horizontal period. Since the address code assigned to the device is mixed in digital form, it is possible to quickly, reliably, and easily discover this terminal device if an unauthorized copy is made through the terminal device. address to prevent unauthorized use.
- DoiIR Personnel 7 (J, IsI for the entire digitalization)
This has the effect that it is easy to convert the address code, and furthermore, it is difficult to find out where the address code is mixed.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing an embodiment of address code mixed traffic according to the present invention, FIG. 2 is a specific circuit diagram of a PN code generation circuit, and FIG. 3 is an I
) A state change diagram showing the change state of the dinomyl register in the N code generation circuit ( ) in a table. Figure 4 is a specific circuit diagram of the address code mixing circuit. Figure 5 is the address at J5 in the composite video signal. Figure 6 is a waveform diagram to explain the code insertion position, Figure 6 is a waveform diagram to explain the correspondence between various signals, Figure 7 is a schematic diagram showing television signal C in units of fields, Figure 8 Figure 9 is a signal diagram showing codes used as star 1 to signals for detection 11, Figure 9 is a signal diagram showing codes used as set signals for detection, Figure 10 is horizontal scanning line numbers. FIG. 3 is an explanatory diagram showing the relationship between , PN code, and address. [Explanation of codes] 1...Address code 8? Human error 2...TV tuner 3...Descrambler 4...Video signal amplification circuit 7...Initialization processing circuit 8...PN code generation circuit 9...Multiple gate formation circuit-26 = 10...Address signal valve 1 circuit 11...Address code gold circuit 12...Address ROM

Claims (1)

[Claims] (1) In a terminal receiving device that outputs a television signal, a storage means for storing an address code assigned to the terminal receiving device, and an initialization process for generating an initial value in response to a synchronization signal of the television signal. means for generating a PN code based on the initial value; accessing the storage means based on the PN code and synchronizing each bit of the address code with a horizontal period of the television signal; 1. An address code mixing device comprising: an address code generating means for generating an address code; and an address code mixing means for mixing each bit of the address code into the television signal.