JPH01233774A - Manufacture of mes type semiconductor device - Google Patents

Abstract

PURPOSE:To form a gate electrode in a self-alignment manner by a method wherein, after a low-impurity region and a high-impurity region have been formed by using a first mask body, the gate electrode is formed by using a second mask body at a part where the first mask body has been removed. CONSTITUTION:An active region 23 is formed on a semiconductor substrate 21; an impurity is implanted by using a first mask body 24; a second region 26 and a drain region 27 as low-concentration impurity regions are formed. Then, a mask 25 on the first mask body 24 is melted; a side wall 28 is formed; an impurity is implanted again; high-concentration impurity regions 29, 30 are formed. Then, the mask 25 is removed; slid individual regions are activated; after that, electrodes 33, 34 are formed. Then, a photoresist 35 is coated; after that, a second mask body 36 is formed; the first mask body 24 on a gate formation region is removed; a gate electrode 37 is formed in a part where the mask body has been removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing an MES type semiconductor device, and particularly to a method of forming a gate electrode thereof.

[Prior Art] As a conventional method for manufacturing this type of MES type semiconductor device,
For example, those shown in FIGS. 2(A) to 2(D) are known. In this conventional manufacturing method, first, a photoresist is applied to the surface of a gallium arsenide substrate 10, and a pattern is formed on the photoresist to obtain a mask 2. Next, using this mask 2, n-type impurity ions are implanted into the surface of the substrate 10 to form an active region 3 (see FIG. 2(A)).

Next, after removing the mask 2 and depositing a high melting point metal such as tungsten by sputtering, a photoresist mask 4 is formed and the high melting point metal is selectively etched away to obtain a gate electrode 5.

Next, using this gate electrode 5 as a mask, n-type impurity ions are implanted again to form a source region 6 and a drain region 7 in a self-aligned manner (see FIG. 2(B)).

Subsequently, the mask 4 is removed, a mask 8 is formed from photoresist, and using this mask 9 and 1O are formed by ion implantation. Thereafter, the mask 8 is removed, silicon dioxide is deposited on the entire surface, and annealing is performed at about 800°C. Thereafter, a source electrode 11 and a drain electrode 12 are formed in ohmic contact with the high impurity concentration region 9.10 (see FIG. 2(D)).

[Problems to be Solved by the Invention] In the above conventional method, the impurity region requires high-temperature annealing after forming the gate electrode. 7. Since 9°10 continues, interfacial stress occurs during annealing due to a difference in thermal expansion coefficient between the substrate and the metal layer, and the Schottky characteristics deteriorate. Furthermore, the gate electrode must be formed of a high-melting point metal that can withstand high-temperature annealing, which poses a problem in that there are many restrictions on the selection of metals that can be used to obtain desired Schottky characteristics. Therefore, it is an object of the present invention to provide a manufacturing method that does not cause deterioration of the characteristics of an MES type semiconductor device, does not cause deterioration of the characteristics of the device, and has a high degree of freedom in metal selection.

[Means for Solving the Problems] The present invention focuses on the fact that a low melting point metal can be used as a material for the gate electrode if the gate electrode is formed after forming an impurity region that requires high-temperature annealing. forming a first mask body on the surface of the semiconductor layer to form a low impurity concentration region on the surface portion of the semiconductor layer and a high impurity concentration region within the low impurity region; and the semiconductor layer around the mask body. forming a second mask body on the surface;
removing the first mask body to expose the surface of the semiconductor layer; depositing a metal layer on the exposed semiconductor layer surface and the second mask body; and forming a gate electrode by separating the semiconductor layer from the semiconductor layer.

[Operations and Effects of the Invention] In the method for manufacturing an MES type semiconductor device described above, after forming a low impurity region and a high impurity region using the first mask body, the second mask body is used to form the first mask. Since the gate electrode is formed on the area where the body was removed, the gate electrode can be formed in self-alignment with the impurity region. Moreover, since the gate electrode is formed after the high-temperature treatment that is essential for forming the impurity region, the gate metal is not exposed to high temperatures and good Schottky characteristics are obtained, making it unnecessary to use a special high-melting point metal. There isn't.

[Embodiment] Next, an embodiment of the present invention will be described with reference to FIGS. 1(A) to 1(J).

FIG. 1A shows a state in which a photoresist mask 22 is formed on a gallium arsenide (GaAs) substrate 21, and then an n-type impurity is ion-implanted to form an active region 23. After this, the mask 22 is removed and the substrate 21
A silicon oxide film 5i02 is formed on the surface of 0 by, for example, the CDV method.
After that, a photoresist mask 25 is formed in a lithography process (see FIG. 1B).

The silicon oxide film 24 is selectively removed by etching using a mask 25 to become a first mask body, and as a result, n-type impurity ions are implanted into the exposed surface of the substrate 21 to form a source as a low impurity concentration region. A region 26 and a drain region 27 are formed (see FIG. 1(C)).

In the next step, the photoresist mask 25 is melted by baking to reach the surface of the substrate 21, thereby forming a sidewall portion. Since the radius of this sidewall portion can be selected empirically by baking time and temperature, only the central portions of the source region 26 and drain region 27 are exposed, and n-type impurity ions are implanted again to form a photoresist. After removing , high impurity concentration regions 29 and 30 are formed (see FIG. 1(D)).

As described above, in this embodiment, only a mask forming step is required when forming the source region 26 and drain region 27.
A mask forming step is not necessary when forming the high impurity concentration regions 29 and 30. Therefore, the number of masks used during manufacturing can be reduced by one.

Next, the mask 25 is removed, a silicon nitride film 31 is deposited on the entire surface by the CDV method, and high-temperature annealing is performed.
3. Perform activation of 26.27.

(See FIG. 1(E)), and a mask 32 that exposes the surface of the high impurity concentration region 29,30 is formed in a lithography process (see FIG. 1(F)). Using the mask 32, ohmic electrodes 33 and 34 are formed by lift-off to obtain the structure shown in FIG. 1(G).

After applying the photoresist 35 again, the mask 32 and the silicon nitride film 31 are removed by etching back until the top surface of the first mask body 24 is exposed (see FIG. 1H). A mask 36 is formed again by a lithography process, and SiO2
Then, the first mask body 24 on the gate formation region is removed by selective etching of SiN (see FIG. 1(I)). 1st
When the mask body 24 is removed, the surface of the substrate 210 is exposed, so a gate metal such as aluminum is formed on the entire surface. (See Figure 1 (J)). Therefore, the photoresist 35 and the mask 36 constitute a second mask body.

As explained above, in this embodiment, the impurity region 28. which requires high temperature annealing. 27. Since the gate electrode 37 is formed after the formation of the 29.degree. Further, it is not necessary to use a heat-resistant material for the gate electrode 37, and the degree of freedom in selecting the metal is increased.

[Brief explanation of the drawing]

FIGS. 1A to 1J are sectional views showing the main steps of an embodiment of the present invention, and FIGS. 2A to 2D are sectional views showing the steps of a conventional example. 21... Substrate, 24... First mask body (silicon oxide film), 26.
27...Source region, drain region (low impurity concentration region), 29.30...High impurity concentration region, 31...
, silicon nitride film, 35... photoresist, 36... second mask body, 37... gate electrode.

Claims (1)

[Scope of Claims] A step of forming a first mask body on the surface of the semiconductor layer to form a low impurity concentration region on the surface portion of the semiconductor layer and a high impurity concentration region within the low impurity region; forming a second mask body on the surrounding surface of the semiconductor layer; removing the first mask body to expose the surface of the semiconductor layer; and connecting the exposed semiconductor layer surface with the second mask body. A method for manufacturing an MES type semiconductor device, comprising the steps of: depositing a metal layer on the semiconductor layer; and peeling off the second mask body from the semiconductor layer to form a gate electrode.