JPH01236498A - Shift register circuit - Google Patents

Abstract

PURPOSE:To attain initialization with the clock signal of one period by providing a clock signal giving means to give a normal phase or opposite phase clock signal to all latch circuits in a serial circuit body in response to the command of the initialization. CONSTITUTION:An EX-NOR circuit 10 is provided instead of the inverter circuit of a conventional circuit and not only a clock signal CLK but also a setting signal SET to designate a timing to generate the signal of the same phase as the clock signal CLK are inputted to the EX-NOR circuit 10. Consequently, by giving the same clock signal CLK is given to all latches in response to the command of the initialization, the data given in response to the clock signal CLK are latched to all latches at the same time. Thus, a shift register circuit can be initialized by one period of the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shift register circuit, and particularly to a shift register circuit that propagates data in synchronization with a clock signal.

[Conventional technology]

FIG. 2 is a circuit diagram showing a conventional shift register circuit used in a semiconductor integrated circuit device. In the figure, 1a to 1d are D-type flip-flops (hereinafter D-F
Abbreviated as F. ) circuits and are connected in series. Reference numeral 2 indicates an input signal line for supplying the input f-taper P to the D-FF circuit 1a, and 2a to 2C indicate the D-FF circuits 1a, 1b, and 1b, respectively.
and Ic.

The node between 1G and 1d, 3 is an output signal line, and 4 is a CLK input signal line to which the clock signal CLK is input, which is directly connected to the odd-numbered D-FF circuits 1a and 1c, and is connected to the O-clock signal. It is connected to even-numbered D-FF circuits 1b and Id via an inverter circuit 5 for inverting CLK. The output end of the inverter circuit 5 is shown as a node 2d. Then, the clock signal CLK is “H”/“
By repeating "L", the input data P applied to the input signal line 2 is sequentially propagated to the D-FF circuits 1a to 1d and output to the output signal line 3.

FIG. 3 is a circuit diagram showing an example of the configuration of D-FF circuits 1a to 1d. In the figure, 6 and 7 are N-type MOS transistors (hereinafter abbreviated as IN-MO8TJ). N-M
A clock signal CLK is applied to the gate of O8T6,
An input signal P is applied to one end. A clock signal CL is applied to the gate of N-MO8T7 via an inverter circuit 8a.
An inverted signal of K is applied, one end is connected to the other end of the N-MO8T6, and a series circuit body of inverter circuits 8b and 8c is connected between the one end and the other end. and,
The through mode/latch mode is switched according to the H/L of the clock signal CLK, and the input data input to the input signal line 2 is output to the signal line 9, and the data on the signal line 9 is output to the signal line 9. or keep it.

Next, the operation will be explained. First, the operation of the circuit shown in FIG. 3 will be explained. When the input signal P is applied, the N-MO8T6 is in a conductive state while the N-MO8T7 is in a non-conductive state during the period when the clock signal CLK is "1", and the input data P is transmitted through the inverter circuits 8b and 8c. It is instantaneously output to the signal line 9 as is (through mode).

On the other hand, during the period when the clock signal CLK is "L", N-MO8T
6 is in a non-conductive state, N-MO8T7 is in a conductive state, and the signal on the signal line 9 at the time when the clock signal CLK becomes "L" is held in the latch consisting of the closed-loop inverter circuits 8b and 8c ( latch mode).

Next, the operation of the shift register circuit shown in FIG. 2 using the above-described -FF circuit will be explained. C.L.
The clock signal CLK applied to the K input signal line 4 is “H”.
'', the D-FF circuit 1a enters the through mode and instantaneously propagates the input data P to the input signal line 2 to the node 2a.Next, when the clock signal CLK becomes "L", the inverter circuit 5 outputs the clock signal. Since CLK is inverted, "H" is input to the D-FF circuit 1b, and the D-FF circuit 1b is inputted with "H".
The FF circuit 1b enters the through mode and instantaneously propagates the data at the node 2a to the node 2b. At this time, since the clock signal CLK which is "YES" is input to the D-FF circuit 1a, the D-FF 1a enters the latch mode and latches the data of the node 2a immediately before the clock signal CLK becomes "L II". are doing.

Next, when the clock signal CLK becomes "H" again, D-F
The F circuit 1C enters the through mode and instantaneously propagates the data at the node 2b to the node 2C. At this time, the clock signal CLK at "L" is input to the D-FF circuit 1b, so it enters the latch mode, and the D-FF circuit 1b latches the data at the node 2b immediately before the clock signal CLK becomes "H". ing. Also, at this time, since the clock signal CLK at "H" is input to the D-FF circuit 1a,
The D-FF circuit 1a is in through mode, and the input signal line 2
instantaneously propagates new data to node 2a. In this way, by alternately repeating "H" and "L" of the clock signal CLK, the shift register circuit
The input data P is sequentially propagated to the output signal line 3. FIG. 4 shows this time chart.

[Problem to be solved by the invention]

Since the conventional shift register circuit is configured as described above, all of the D-FF circuits 1a to 1d are brought into a state where 0" or "1" is latched (hereinafter referred to as initialization).
In order to do this, the clock signal CLK must be input repeatedly for many cycles with the input data P fixed at 0 or 1, and each D-FF circuit must latch 0 or 1n in turn. However, if the number of bits is large, there is a problem that it takes a long time to initialize the shift register circuit.

This invention was made in order to solve the above-mentioned problems, and an object thereof is to obtain a shift register circuit that can be initialized with a one-cycle clock signal.

[Means to solve the problem]

The shift register circuit according to the present invention includes a series circuit body in which a plurality of latch circuits are connected in series to latch data in response to a clock signal, and a series circuit body in which a plurality of latch circuits that latch data in response to a clock signal are connected in series; and the other to the odd-numbered latch circuits in the series circuit body, and the other to the even-numbered latch circuits, and the positive phase or negative phase clock signal is applied to all the latch circuits in the series circuit body in response to an initialization command. The configuration includes a clock signal providing means for providing a clock signal.

[Effect]

The clock signal applying means in this invention applies the same clock signal to all latches in response to an initialization command,
In response to this clock signal, applied data is latched into all latches at once.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, the difference from the conventional circuit shown in FIG. 2 is that an EX-NOR circuit 10 is provided in place of the inverter circuit 5;
- Not only the clock signal CLK but also a set signal SET specifying the timing for generating a signal in phase with the clock signal CLK is input to the NOR circuit 10. The other configurations are the same as the conventional circuit.

Next, the operation will be explained. The set signal SET is set to "L". In this case, the EX-NOR circuit 10 outputs "T1'" when the clock signal CLK is "L", and outputs "L" when the clock signal @CLK is "H". Output. in this way,
When the set signal @SET is "L'°, the EX-NOR circuit 10 generates a signal with the opposite phase to the clock signal CLK. In this way, when the set signal @SET is L'', the EX-NOR circuit 10
The R circuit 10 operates as an inverter circuit, and therefore the present circuit operates as a shift register circuit similar to the conventional circuit shown in FIG.

Next, the case where the set signal MSET is "HII" will be explained. In this case, the EX-NOR circuit 10 outputs "L" when the clock signal CLK is "LIT", and outputs "H" when the clock signal CLK is "HH". ''. In this way, when the set signal SET is "H", the EX-NOR circuit 10
outputs a signal that is in phase with the black/red signal CLK.

The case of initializing the shift register circuit shown in FIG. 1 will be described below. Set signal SET as initialization command
is set to “H”. Then, the clock signal CLK is “H”
Then, H'' is given to the D-FF circuits 1a to 1d,
D-FF circuits 1a to 1d are in through mode. In this state, for example, if input data P is "0", D
-FF circuit 1a is connected to node 2a, D-FF circuit 1b is connected to node 2b, D-FF circuit 1C is connected to node 2C, D-FF
The F circuit 1d instantaneously propagates "0" to the output signal line 3. Then, when the clock signal CLK becomes L'',
D-FF circuits 1a to 1d are in latch mode, and D-FF
The F circuits 1a to 1d latch 0''.In this way, one cycle of the clock signal CLK rD-FF circuits 1a to 1
d can all be latched at "0". That is, the shift register circuit can be initialized in one cycle of the clock signal CLK.

In the above embodiment, a D-FF circuit that enters the latch mode in response to the "L" level of the clock signal CLK is used, but a D-FF circuit that enters the latch mode in response to the "H" level of the clock signal CLK is used.
More generally, the present invention can be constructed using a latch circuit that latches data in response to a clock signal. Furthermore, it goes without saying that the series circuit body of the latch circuit may have any number of stages.

Further, in the above embodiment, EX-N is used to generate signals having the opposite phase and the same phase as the clock signal CLK in response to shift operation and initialization commands, respectively.

Although 8 circuits were used, this function can also be realized using Haku's logic circuit. Furthermore, during initialization, all D-FF circuits 1a to 1
The signal given to clock signal CLK may not be in phase with clock signal CLK, but may be a signal in opposite phase. This can be achieved, for example, by inserting an inverter into the signal line of clock signal CLK in FIG. . In short, in response to a shift operation command, one of the positive-phase and negative-phase clock signals is applied to an odd-numbered latch circuit in the series circuit, and the other is applied to an even-numbered latch circuit, and in response to an initialization command. Any means may be used as long as it can provide a positive phase clock signal or a negative phase clock signal to all latch circuits in the series circuit body.

(Effects of the Invention) As described above, according to the present invention, in response to an initialization command, the positive phase or negative phase zero signal is applied to all the latches in the series circuit of latches. , the shift register circuit can be initialized in one cycle of the clock signal.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional shift register circuit, and Fig. 3 is a D-F circuit diagram.
FIG. 4 is a circuit diagram showing an example of the configuration of the F circuit. FIG. 4 is a time chart showing the operation of the conventional shift register circuit shown in FIG. In the figure, 1a to 1d are D-FF circuits, 10 is EX-
In the NOR circuit, SET is a set signal, and CLK is a clock signal. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 4

Claims (1)

[Claims] (1) A series circuit body in which a plurality of latch circuits are connected in series to latch data in response to a clock signal, and one of the positive phase and negative phase clock signals is connected to the series circuit body in response to a shift operation command a clock signal providing means that applies the clock signal to an odd-numbered latch circuit and the other to an even-numbered latch circuit, and applies the positive phase or negative phase clock signal to all latch circuits in the series circuit body in response to an initialization command; A shift register circuit comprising: