JPH01236655A - Thin film field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to manufacture a TFT having a small parasitic resistance and a small parasitic capacity at a high yield by a method wherein lead-out electrodes having a selective etching property with a semiconductor thin film and a semiconductor thin film doped with an impurity for making contact with the semiconductor thin film are provided between the impurity- doped semiconductor thin film and source and drain electrodes. CONSTITUTION:A semiconductor thin film 5 doped with an impurity for making contact with a semiconductor thin film 6 is formed between a gate insulating film 3 and the film 6 excepting its channel part. Moreover, lead-out electrodes 4 are provided on the upper part, which includes part of the lower part of the impurity doped film 5, of the film 3 and the electrodes 4 have a selective etching property with the film 6 and the impurity-doped film 5. Accordingly, the electrodes 4 work as a stopper at the time of etching of the films 5 and 6 and the etching is stopped there. Thereby, a thin film field effect transistor (TFT) having a small parasitic resistance and a small parasitic capacity can be obtained at a high yield.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film field effect transistor that can be used in display devices such as liquid crystal displays, and a method for manufacturing the same.

BACKGROUND OF THE INVENTION In recent years, research and development of thin film field effect transistors (hereinafter referred to as 'rFTs) used in active matrix substrates for liquid crystal displays has become active.

Hereinafter, a conventional TPT will be explained with reference to the drawings. Figure 3 is a schematic cross-sectional view of a conventional TPT.
is, for example, a translucent insulating substrate such as a glass substrate. Reference numeral 2 denotes a gate electrode, on which a gate insulating film 3 made of silicon nitride or the like is formed.

Furthermore, a semiconductor thin film 6 that will become an active layer is deposited on top of it.
A source electrode 8 and a drain electrode 9 are provided on the surface thereof. A semiconductor thin film 5 doped with impurities is provided between the source electrode 8 and drain electrode 9 and the semiconductor thin film 60 to improve contact. Reference numeral 7 denotes a puffy base film for protecting the semiconductor thin film 6.

The operation of the TPT configured as described above will be explained below. First, when a positive voltage is applied to the gate electrode 2, electrons are induced in the semiconductor thin film 6, and a low resistance layer, that is, a channel is formed between the semiconductor thin film 6 and the gate insulating film 3.In this state, the source electrode 8 and When a voltage is applied between the drain electrodes 9, a current flows through the channel. Here, when the voltage applied to the gate electrode 2 is cut off, the channel disappears and returns to the original high resistance layer. Therefore, the current flowing between the source electrode 8 and the drain electrode 9 is drastically reduced. In this way, the current flowing between the source electrode 8 and the drain electrode 9 can be controlled by the voltage applied to the gate electrode 2.

However, in the configuration shown in FIG. 3, parasitic resistance such as the resistance 10 of the semiconductor thin film from the source electrode 8 or drain electrode 9 to the channel, and the overlapped portion between the gate electrode 2 and the source electrode 8t or the drain electrode 9 are caused. Since a parasitic capacitance such as an overlap capacitance 11 is generated due to the overlapping capacitance 11 caused by In order to solve the above-mentioned problems, a TPT with a configuration as shown in Fig. 4 has been proposed. Hereinafter, referring to the drawings, a TPT that has solved the above-mentioned problems is proposed.
I will explain about it. Figure 4 solves the above problems and 7! (
FIG. 3 is a schematic cross-sectional view of TPT. Figure 3 Conventional TPT
The same numbers are given to the parts corresponding to the structure of the third part.
The difference from the figure is that the impurity-doped semiconductor thin film 6 is formed between the gate insulating film 3 and the semiconductor thin film 60, and the impurity-doped semiconductor thin film 6 directly above the gate electrode 2 is removed in a self-aligned manner. This is what is being done.

By adopting the above configuration, the channel portion and the impurity-doped semiconductor thin film 6 are directly connected, so that the parasitic resistance 10 is reduced. Further, since there is no overlap between the gate electrode 2 and the semiconductor thin film 6 containing impurities, the parasitic capacitance 11 is also reduced.

Problems to be Solved by the Invention When the above configuration is adopted, the semiconductor thin film 6 must be formed after removing the impurity-doped semiconductor thin film 6 in the channel region. The semiconductor thin film 6 doped with impurities and the original semiconductor thin film have very similar physical properties and do not have selective etching properties. Therefore, when the semiconductor thin film 6 is etched, the semiconductor thin film 6 doped with impurities is also etched at the same time.Conventionally, the semiconductor thin film 6 doped with impurities is deposited thickly in advance to account for the overetching. The etching of the thin film 6 was controlled by time. However, with this method,
There is a problem that good contact with the source electrode 8 and drain electrode 9 cannot be made because the semiconductor thin film 6 remains due to under-etching or the semiconductor thin film 6 doped with impurities disappears due to over-etching. It has been difficult to manufacture large-area active matrix substrates uniformly and with a high yield using this method.

In view of the above-mentioned problems, the present invention provides a thin-film field-effect transistor and a method for manufacturing the same, which can uniformly manufacture high-performance TPTs with small parasitic resistance and capacitance at a high yield.

Means for Solving the Problems In order to solve the above problems, the TPT of the present invention has a structure in which a semiconductor thin film doped with an impurity to make contact with the semiconductor thin film connects the gate I/insulating film and the channel part of the semiconductor thin film. The gate insulating film has an extraction electrode formed between the semiconductor thin film and the lower part of the impurity-doped semiconductor thin film. It has selective etching properties.

Furthermore, in order to manufacture the TPT having the above structure uniformly and with high yield, the TPT manufacturing method of the present invention is to form an extraction electrode after forming a gate insulating film, and then to form a semiconductor thin film doped with impurities on the entire surface. After removing the impurity-doped semiconductor thin film in the part that will become the channel, a semiconductor thin film is formed on the entire surface, and the semiconductor thin film and the impurity-doped semiconductor thin film are successively etched into a predetermined shape using the same mask and the same etchant. Then, a source electrode and a drain electrode are formed on the exposed extraction electrode.

Function The present invention enables the semiconductor thin film to be formed into a predetermined shape by providing an extraction electrode having selective etching properties with the semiconductor thin film between the semiconductor thin film doped with impurities for making contact with the semiconductor thin film, and the source and drain electrodes. When etching into the shape, the semiconductor thin film 60 is etched at the same time.
The underlying impurity-doped semiconductor thin film can also be removed, making it possible to easily manufacture high-performance TPTs with low parasitic resistance at high yields.

In addition, by removing the impurity-doped semiconductor thin film directly above the gate electrode to a size approximately equal to that of the gate electrode, it is possible to manufacture a high-performance TFτ with no overlap capacitance between the gate electrode and the source or drain electrode. can.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic cross-sectional view of a TPT according to an embodiment of the present invention. Components corresponding to the conventional configuration in FIG. 4 are given the same numbers.

Figure 4 What is the difference between semiconductor thin film doped with impurities 6
are formed in the same pattern only directly under the semiconductor thin film e, and the extraction electrode 4 is formed from the bottom of the impurity-doped semiconductor thin film 60 to the bottom of the source electrode 8 and drain electrode 9.

Next, an embodiment of the TPT manufacturing method of the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of the TFTL:D manufacturing method of the present invention. First, as shown in FIG. 2 B, a silicon nitride film is deposited as a gate insulating film 3 on a glass substrate as a light-transmitting insulating substrate 1 on which a gate electrode 2 has been formed in advance, and then a silicon nitride film is deposited as a gate insulating film 3 under the glow of a mixed gas of nitrogen, ammonia, and silane O. It is deposited to a thickness of 4,000 people using the discharge decomposition method. Note that the gate electrode 2 is formed by sputtering chromium onto a glass substrate.
After depositing titanium to a thickness of 1,000 wafers, it was patterned into a predetermined shape using ordinary photolithography.Next, as shown in Figure 2, titanium was deposited to a thickness of 1,000 wafers over the entire surface. Only the portions that will become the electrodes and drain electrodes are left using photolithography to form the extraction electrodes 4. Further, as shown in FIG. A portion of the phosphorus-doped amorphous silicon film is selectively etched. Here, amorphous silicon was used as the semiconductor thin film, phosphorus was used as an impurity, and the film was deposited to a thickness of SOO by glow discharge decomposition of phosphine and silane.

Thereafter, after cleaning the part where the channel will be formed with an IF bath solution, as shown in FIG. So, 2000 people and 100 people respectively.
After being deposited to a thickness of 0.5 mm, selective etching is performed in the same pattern into a predetermined shape as shown in FIG.

Finally, as shown in Figure 2 f, aluminum is deposited on the entire surface to a thickness of 8,000 mm, and then patterned into a predetermined shape by photolithography to form a source electrode 8 and a drain electrode 9, completing the process. .

As described above, according to this embodiment, when patterning an amorphous silicon film, the phosphorus-doped amorphous silicon film can also be removed at the same time, making it possible to easily create a high-performance TFT.
PT can be manufactured with high yield.Next, other embodiments of the present invention will be described with reference to the drawings.

FIG. 2gNII is another embodiment of the method for manufacturing TPT of the present invention. As shown in FIG. 2g, the steps up to the point where an amorphous silicon film doped with phosphorus is deposited as the semiconductor thin film 5 whose entire surface is doped with impurities are the same as in the previous embodiment described above. Next, as shown in the second diagram,
A photosensitive resin film 12 is applied onto the impurity-doped semiconductor thin film 5 using a spinner and prebaked, and then exposed to ultraviolet light from the back side using the gate electrode 2 as a mask.

At this time, the semiconductor thin film 6 doped with impurities must be thin enough to transmit ultraviolet light having sufficient intensity to expose the photosensitive resin film 12. Used in this example &
In the case of IJ-doped amorphous silicon, it was possible to sufficiently transmit ultraviolet light and expose the photosensitive resin film 12 with a film thickness of 500 Å or less. Furthermore, when using this method, the gate electrode 2 must have sufficient light-shielding properties against the ultraviolet light that exposes the photosensitive resin film 12.

In this example, a chromium thin film with a thickness of 1000 mm was used, which was sufficient as a mask material. Furthermore, in this embodiment, a negative resist 0MR83 is used as the photosensitive resin film 12.
However, this is not limited to negative resists; for example, a positive resist can be applied, exposed to light from the back using gate electrode 2 as a mask, and then treated with ammonia vapor and developed. With this, it is possible to obtain the same effect as a negative resist. Next, as shown in FIG. 2, the photosensitive resin film 12 directly above the gate electrode 2 is removed by development, and after post-baking, a semiconductor thin film 6 doped with impurities is formed using the photosensitive resin film 12 as a mask. Remove by etching. Thereafter, as shown in FIG. 2J, a structure is completed in which the photosensitive resin film 12 is removed and the impurity-doped semiconductor thin film 6 is removed in a self-aligned manner with respect to the gate electrode 2. Thereafter, final completion is achieved as shown in FIG. There is no capacitance and the source electrode 8 and drain electrode 9
High-performance TF with extremely small capacitance between gate electrode 2 and gate electrode 2
Furthermore, since the manufacturing method uses back exposure using the gate electrode 2 having a light-shielding property as a mask, it can be easily manufactured.

Although amorphous silicon is used as the semiconductor thin film 5.6 in the above embodiment, it is not limited to amorphous silicon, and any thin film having a semiconductor function may be used. For example, polycrystalline silicon can be used. When this material is used, a high mobility can be expected, so a TPT with a high operating frequency can be obtained. Further, in this case, arsenic, antimony, boron, aluminum, indium, etc. can be considered as impurities to be doped into the semiconductor thin film.

Further, in the above embodiment, titanium is used as the lead-out electrode 4, but titanium is not limited to titanium, and has sufficient selective etching properties with the semiconductor thin film 6 and the semiconductor thin film 6 doped with impurities, and is free from impurities. Any material that does not create a potential barrier that would impede the flow of current when brought into contact with the doped semiconductor thin film 6 may be used. For example, metals that easily form silicide, such as aluminum and molybdenum, can be considered.

Effects of the Invention As is clear from the above description, the present invention includes an extraction electrode between a semiconductor thin film doped with impurities for making contact with the semiconductor thin film, and a source electrode and a drain electrode, and the extraction electrode is selected from the semiconductor thin film. Since it has an etching property, the extraction electrode acts as a stopper during etching of the semiconductor thin film, and etching is stopped there, making it possible to easily manufacture TPT at a high yield.

In addition, in the 72 devices of the present invention, a semiconductor thin film doped with impurities is formed adjacent to the channel portion, so even if a relatively high resistance semiconductor material such as amorphous silicon is used for the semiconductor thin film, parasitic A TPT with low resistance can be realized.

Furthermore, the TPT of the present invention has an extremely small parasitic capacitance between the gate electrode and the source and drain electrodes by removing the impurity-doped semiconductor thin film directly above the gate electrode in a self-aligned manner with respect to the gate electrode.
can be realized. Furthermore, since the manufacturing method uses backside exposure using the gate electrode as a mask, it can be manufactured easily.゛

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of an embodiment of the TPT of the present invention,
Fig. 2a Nf is a sectional view showing an embodiment of the TPT manufacturing method of the present invention, Fig. 2gN! ! 1 is a cross-sectional view showing another embodiment of the manufacturing method of the present invention, FIG. 3 is a schematic cross-sectional view of a conventional TPT, and FIG. 4 is a schematic cross-sectional view of a conventional TPT with small parasitic elements.
It is a typical sectional view of T. 1... Translucent insulating vaporized plate, 2... Gate electrode, 3... Gate insulating film, 4...
Extraction electrode, 5... Semiconductor thin film doped with impurities, 6... Semiconductor thin film, 7...
・Passivation film, 8...Source electrode, 9
...Drain electrode, 1o... Parasitic resistance, 11... Parasitic capacitance, 12... Photosensitive resin film. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
---Transparent surname extinct version δ---Saone Denpei 9-11 Dongyin Hanpei Figure 1 Figure 2 Do (d) Figure 2 (e) and (f) Figure 2 Figure 2 (the law of nature

Claims (4)

[Claims] (1) A gate electrode provided on the surface of a light-transmitting insulating substrate, a gate insulating film formed to cover at least the gate electrode, and a gate insulating film formed on the gate insulating film including at least a portion directly above the gate electrode. a semiconductor thin film doped with an impurity formed in a region other than the channel region between the gate insulating film and the semiconductor thin film, and the gate insulating film including at least a part of the lower part of the semiconductor thin film doped with the impurity. and a source electrode and a drain electrode formed including at least the extraction electrode, and the extraction electrode can be selectively etched with the semiconductor thin film and the impurity-doped semiconductor thin film. A thin film field effect transistor characterized in that it is made of a material. (2) The thin film field effect transistor according to claim 1, wherein a portion of the impurity-doped semiconductor thin film immediately above the gate electrode has a portion approximately the same size as the gate electrode. (3) forming a gate electrode on the surface of a light-transmitting insulating substrate; forming a gate insulating film to cover at least the gate electrode; and excluding at least the area immediately above the gate electrode on the gate insulating film A step of forming an extraction electrode that will become part of the source electrode and a drain electrode in a portion, a step of forming a semiconductor thin film doped with an impurity over the entire surface, and a step of removing the semiconductor thin film doped with the impurity in a portion that will become a channel. a step of forming a semiconductor thin film to serve as an active layer on the entire surface; a step of etching the semiconductor thin film and the impurity-doped semiconductor thin film into a predetermined shape so that a part of the extraction electrode is exposed; A method for manufacturing a thin film field effect transistor, comprising the step of forming a source electrode and a drain electrode including the upper part of the extraction electrode. (4) in the step of removing the impurity-doped semiconductor thin film in the portion that will become the channel, a step of applying a photosensitive resin film over the entire surface, and a step of exposing the gate electrode to ultraviolet light from the back surface using the gate electrode as a mask; A process of developing and removing the photosensitive resin film in the areas not exposed to light, and etching away the semiconductor thin film doped with the impurity using the photosensitive resin film as a mask to remove the impurity in the area directly above the gate electrode. removing the doped semiconductor thin film in a self-aligned manner with respect to the gate electrode, the gate electrode being made of a material that has a light-shielding property at least against ultraviolet light to which the photosensitive resin film is sensitive. A method for manufacturing a thin film field effect transistor according to claim 3.