JPH01237719A - Data logical sum compressing circuit - Google Patents

Abstract

PURPOSE:To easily obtain OR-compressed data and to shorten a processing time by latching the data from a CPU to a register, OR-compressing the data with an OR circuit part and further, reading a buffer which is connected to the OR circuit part, with the read signal of the CPU. CONSTITUTION:A compressing circuit is composed of a CPU 1, a register 5 to latch the data from this CPU, an OR circuit part 6 to be the set of OR gates and a buffer 7 for which the read from the CPU 1 can be executed. Thus, the data are latched by a write signal 3 from the CPU 1 in the register 5 to be connected to a data bus 2 of the CPU 1. Next, latch data 8 to be latched are outputted to the OR circuit part 6 and OR operation with the arbitrary bit of the data 8 is executed. Then, an operated result is outputted to the buffer 7. The buffer 7 outputs the result which is operated in the circuit part 6, to the data bus 2 with use of a read signal 4 from the CPU 1. Accordingly, a software burden on the CPU by a program is erased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data operation circuit using a central processing unit (CPU), and particularly to a data OR operation circuit.

[Prior Art] Conventionally, this type of data OR compression has been performed by a CPU program.

[Problem to be solved by the invention]

The above-described conventional data OR compression is performed by a CPU pulldown, which has the disadvantage of placing a burden on the software and requiring a large number of program steps and processing time.

[Means to solve the problem]

According to the present invention, there is a register that latches data from the central processing unit, an OR circuit section connected to the register and composed of a group of OR gates, and a read circuit section connected to the OR circuit section and connected to the central processing unit. A data OR compression circuit is obtained which includes a buffer that outputs data in the form of a signal.

〔Example〕

Next, the present invention will be described in more detail with reference to the drawings showing one embodiment of the present invention.

Referring to FIG. 1, the data OR compression circuit according to one embodiment of the present invention includes a CPU, a register 5 that latches data from the CPU 1, an OR circuit section 6 that is a collection of OR gates, and a read circuit from the CPU. It is equipped with a buffer 7 that can be used.

The register 5 connected to the data bus 2 of the CPUI is
Data is latched by write signal 3 from PUI.

Latch data 8 latched by register 5 is output to OR circuit section 6. The OR circuit section 6 is a collection of OR gates, performs an OR operation between arbitrary bits of the latch data 8, and outputs the result to the buffer 7. The buffer 7 outputs the calculation result of the OR circuit section to the data bus 2 in response to the read signal 4 from the CPU.

In this way, by writing data from the CPUI to the register 5 and then reading the buffer 7, it is possible to obtain data that has been ORed between arbitrary bits of the data and whose bit length has been compressed. can.

〔Effect of the invention〕

As explained above, according to the present invention, data from the CPU is latched in a register, OR-compressed by the OR circuit, and the buffer connected to the OR circuit is
By reading with the read signal, the result of ORing the data can be easily obtained. Therefore, there is an effect that the software burden due to the CPU program that has been required up to now can be eliminated and the processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1: CPU, 2: Data bus, 3 Write signal, 4: Read signal, 5: Register, 6: OR circuit section, 7: Buffer, 8: Latch data. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] a register that latches data from the central processing unit; an OR circuit section connected to the register and composed of a group of OR gates; and an OR circuit section connected to the OR circuit section that latches data from the central processing unit. 1. A data OR compression circuit comprising: a buffer for outputting .