JPH01243591A - Semiconductor device - Google Patents

Abstract

PURPOSE:To change a current between a drain and a source stepwise with respect to a gate voltage by providing a plurality of conductive layers between a gate electrode and a drain electrode. CONSTITUTION:An n type channel region 2 is provided on the principal plane of a semi-insulating GaAs substrate 1 and a laminate conductive region 10 including n type GaAs layers 9 and undoped semi-insulating GaAs layers 8 alternately laminated is provided on the side of a drain of the region 2. Thus, a channel structure located between a gate and the drain is constructed with the alternately laminated conductive layers and semi-insulating layers, the number of the conductive layers covered with a depletion layer is changed discontinuously with respect to gate voltage and hence a current flowing between a source and the drain is also changed in a discontinuous stepwise manner.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, particularly a semiconductor device for a multi-level logic circuit, and relates to a Schottky gate field effect transistor (hereinafter referred to as GaAs-MESF) using GaAs.
It is called ET. ) relates to a technique effective when applied to a semiconductor device configured by

[Conventional technology]

Conventionally, GaAs-MESFETs have not been used as devices for multilevel logic circuits, but recently a resonant tunnel real electron transistor (RHET) using a double-barrier quantum gate structure has been proposed and prototyped. . The GaAs-MESFET is described in "Ultrahigh Speed Compound Semiconductor Device, Baifukan, P59, Figures 3 and 2". Also, regarding resonant tunneling hot electron transistors, rJph, J, Appl.

Phys, 24. PP, L853-L854 (198
5) J or “Solid State Technology (
solid 5tate te-chnology
) Japanese edition, January 1988 issue, pages 35-40.

[Problem to be solved by the invention]

As mentioned above, the resonant tunnel real electron transistor uses a double well quantized in energy units in the base and emitter parts, so its collector current becomes discrete with respect to the base voltage, and the multivalued logic circuit It can be used as a device for However, the operating temperature is significantly lower than room temperature.

An object of the present invention is to provide a semiconductor device suitable for a multivalued logic circuit in which the drain (or collector) current changes stepwise with respect to the gate (or base) voltage.

Another object of the present invention is to provide a semiconductor device suitable for a multivalued logic circuit that can operate at room temperature or higher.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

The GaAs-MESFET for multilevel logic circuits of the present invention has a single conductive layer existing between the gate and drain of a conventional GaAs-MESFET, that is, an nlGaAs layer extending to a depth of about 62 μm, at a predetermined interval. It has a structure in which a semi-insulating GaAs layer (semi-insulating layer) is provided, and n-type GaAs layers and undoped semi-insulating GaAs layers are alternately stacked to provide a laminated conductive region.

[Effect]

According to the above-mentioned means, in the conventional Schottky gate field effect transistor, the current flowing between the source and drain depends on the thickness of the conductive region (channel) under the gate electrode. By applying a voltage to the electrode, the width of the depletion layer extending below the gate electrode is changed, modulating the thickness of the channel and controlling the current between the source and drain. In contrast, the GaAs-M of the present invention
The ESFET has a structure in which the current between the source and drain depends not only on the thickness of the channel under the gate electrode but also on the number of conductive layers that are not covered by the depletion layer between the gate and the drain. That is, the GaAs-MESF of the present invention
In ET, the structure of the channel between the gate and drain is an alternating stack of conductive layers and semi-insulating layers, so the number of conductive layers covered by the depletion layer varies discontinuously with respect to the gate voltage. Therefore, the source-drain current also shows a discontinuous step-like change accordingly.

Due to its electrical characteristics, the present invention becomes a semiconductor device suitable for multivalued logic circuits.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a GaA for multivalued logic circuit according to an embodiment of the present invention.
FIGS. 2 to 5 are cross-sectional views showing an example of the GaAs device manufacturing method of the present invention in the order of steps, and FIG. A third cross-sectional view showing a state in which a conductive region is formed.
The figure is a cross-sectional view showing a state where a channel region is formed on the main surface of a GaAs substrate, FIG. 4 is a cross-sectional view showing a state where a source region and a drain region are formed on the main surface of a GaAs substrate, and FIG. A schematic cross-sectional view showing a depletion layer in
FIG. 6 is a graph showing the theoretical current-voltage characteristics of the GaAs device of the present invention.

As shown in FIG. 1, in the GaAs device according to this embodiment, an n-type channel region 2 is provided on the main surface of a semi-insulating GaAs substrate 1. As shown in FIG.

Further, on the right side of this channel region 2, that is, on the drain side, an n-type GaAs layer 9 and an undoped semi-insulating GaAs layer 9 are formed.
Laminated conductive regions 10 are provided in which As layers 8 are alternately stacked. The n-type GaAs layer 9 has the same composition as the channel region 2. Then, n
A ♦-shaped source region 3 and drain region 4 are provided separately.

On the other hand, a Schottky gate electrode 5 made of, for example, tungsten silicide (W5 SI 3 ) is provided on the surface of the channel region 2, and a gap between the gate electrode 5 and the semi-insulating GaAs base 1 is provided. A Schottky barrier is formed. Further, the main surfaces of the gate electrode 5 and the semi-insulating GaAs substrate l are, for example, 5iO
It is covered with a passivation film 7 such as a Si3N4 film or a Si3N4 film. This passivation film 7 has an opening corresponding to a portion of the source region 3 and drain region 4, and an ohmic electrode 6 is provided in this opening. These ohmic electrodes 6 are connected to source electrodes 11 . The drain electrode 12 is made of a laminated film in which, for example, a gold (Au)-germanium (Ge) alloy film, a nickel (Ni) film, and an Au film are laminated in this order.

In the GaAs device according to this example, the source (
The source electrode 11) is grounded, and the drain (drain electrode 1
2) When a positive voltage is applied to
, passes through the channel region 2 under the gate electrode 5 and enters the source region 3 . Here, the magnitude of the source-drain current is mainly determined by nft3GaAs, which can flow current.
It depends on the number of layers 9. As a negative voltage is applied to the Schottky gate electrode 5, as shown in FIG. 5, the depletion layer 13 under the gate electrode 5 expands and blocks the exit of the n-type GaAs layer 9 from the side closest to the surface. I'm leaving. Since the semi-insulating CaAs layer 8 and the n-type GaAs layer 9 are arranged as shown in FIG.
With respect to the voltage of the gate electrode 5), the number of n-type GaAs layers 9 whose exits are not blocked by the depletion layer 13, that is, the number of n-type GaAs layers 9 through which current can flow, changes discontinuously. Therefore, the source-drain current with respect to the gate voltage changes stepwise, as shown in the current-voltage characteristics showing the correlation between the drain-source current and the gate-source voltage (V*-: unit V) in Figure 6. Change. As shown in the graph, the solid line portion is a curve based on calculated values, and the broken line portion is a curve based on estimation.

As a result, the GaAs-MESFET of the present invention becomes a device suitable for multivalued logic.

Here, an example of device calculation showing the characteristics shown in FIG. 6 will be described. The dimensions of each part are shown in FIG.

Source-drain current l. is given by equation (1).
It will be done.

■.

zo=□・・・(1) Here, R is the resistance of the channel layer, and V411 is the resistance of the drain layer.
The resistance R of the channel layer, which is 1v in this example at the source voltage
(unit Ω) is expressed as equation (2).

0, 12-d n (d) Here, d is the depletion layer width (unit: μm), n is 0°1.2,
It is 3.4.

The depletion layer width d is (3)2.

Here, E is the dielectric constant of GaAs, q is the elementary charge, and q is the barrier potential, which is 0.8 in this example. Further, N is the impurity concentration of the channel region, and in this example, 2.
It is 3X10"7cm".

Further, in this example, the gate length is 1 μm, and the length of the laminated conductive region 10 is 1 μm. The laminated groove IIT region 10 is provided with an n-type GaAs layer 9 as the lowest layer, and an undoped semi-insulating GaAs layer 8 on top of the n-type GaAs layer 9.
．． n-type GaAs layer9. Undoped semi-insulating GaAs layer 8
and are provided alternately. Four n-type GaAs layers 9 are formed, and the top layer is an undoped semi-insulating GaAs layer 8.

The uppermost undoped semi-insulating GaAs layer 8 has a thickness T that is thicker than the thickness L of the other three undoped semi-insulating GaAs layers 8.
It becomes. Further, each n-type GaAsJi 9 has the same thickness a. Each dimension in this example is t
= 150 people, T = 550 people, a = 50 people.

Therefore, the total thickness of the laminated conductive region 10 is 1
The channel region 2 in this example has a very thin resistivity ρ of 0.05 Ωcm.

According to such a C;aAs-MESFET, as can be seen from the characteristic curve of FIG. 6, it is possible to select a plurality of dark values, and it can be used as a device for multivalued logic.

Next, the CaA according to this embodiment configured as described above will be explained.
A method for manufacturing the s device will be explained.

As shown in FIG. 2, on a semi-insulating GaAs substrate 1,
For example, n-type GaAs layers (conductive layers) 9 and undoped semi-insulating GaAs layers (semi-insulating layers) 8 are epitaxially grown alternately. The respective thicknesses a, t, and T are, for example, the former n-type GaAs N9 for 50 people,
The latter is made thicker, such that the semi-insulating GaAs layer 8 of the latter is 150 mm thick. After forming the four n-type GaAs layers 9, the uppermost semi-insulating GaAs layer 8 is made 550 thick. This may be determined in relation to the expansion of the depletion layer 13 that occurs when a voltage is applied to the gate electrode 5. Also, n
The impurity concentration of the GaAs layer 9 is, for example, 2.3×1
0"/cm'. The laminated conductive region 10 formed by alternately laminating the n-type GaAs layer 9 and the semi-insulating GaAs layer 8 has a total of 1200 layers.

Next, as shown in FIG. 3, a photoresist (not shown) in a predetermined shape is formed on the surface of the semi-insulating GaAs substrate 1, and this is used as a mask to
ion implantation of shaped impurities to form a long laminated conductive region 1
0 is formed, and n-shaded regions 14 are formed at both ends of this laminated conductive region 10, respectively. Also, both n-type regions 1
For example, protons are ion-implanted using a photoresist having a predetermined shape as a mask on the outside of the semiconductor device 4 to form an isolation region 15 for isolating devices. Thereafter, annealing is performed to electrically activate the n1il region 14 and inactivate the isolation region 15. Note that a part of this n-shaded area 14 is used as a channel. Further, the impurity concentration of this n-shaded region 14 is the same as that of the n-type CaAs layer 9.

Next, a Schottky gate electrode 5 is formed on the left end of the laminated conductive region 10. This gate electrode 5 is formed so that its length is 1.0 μm. Thereafter, using this gate electrode 5 and a photoresist having a predetermined shape as a mask, ions of an n-type impurity such as Si are implanted at a relatively high energy and high dose. Next, after removing the photoresist, annealing is performed to form a source region 3 and a drain region 4.

Thereafter, as shown in FIG. 1, a passivation film 7 is formed over the entire surface, and predetermined portions of the passivation film 7 are etched to form openings above the source region 3 and drain region 4.

Through this opening, Au-Ge, Ni, and Au are sequentially deposited onto the source region 3 and drain region 4 to form a source electrode 11 consisting of an ohmic electrode 8ii6 and a drain electrode i.
12 is formed, thereby completing the intended GaAs device.

According to such an embodiment, the following effects can be obtained.

(1) GaAs-MESFET for multi-value logic circuit of the present invention
Since a laminated conductive region having multiple conductive layers is provided between the gate and the drain, current may or may not flow through each of the conductive layers as the depletion layer expands as the gate voltage changes. Therefore, it is possible to obtain the effect that the change in the drain-source current with respect to the gate voltage can be made stepwise.

(2) According to (1) above, the GaAs-MESFET is
Since the change in the drain-source current with respect to the gate voltage is step-like, it is possible to construct a device for a multivalued logic circuit.

(3) The GaAs-MESFET of the present invention is different from the conventional GaAs-MESFET.
As the As-MESFET has a structure in which a laminated conductive region is provided between the channel and drain region directly under the gate electrode, it is not required to be used in a special temperature range.
The effect is that it can be used in the same temperature range as before.

(4) Since the GaA, s-MESFET of the present invention can be manufactured using established GaAs-MESFET manufacturing technology, etc., it can be manufactured with good reproducibility.

(5) According to (1) to (4) above, according to the present invention, a GaAs-MESFET for multivalued logic circuits that can be used at room temperature
The synergistic effect is that it can be manufactured at low cost.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

The above explanation will mainly focus on the invention made by the present inventor, which is the application field of GaAs-MESF.
Although the case where the present invention is applied to the ET manufacturing technology has been described, the present invention is not limited thereto.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

According to the present invention, as a result of changing the conductive layer between the gate electrode and the drain bridge from the conventional single layer to multiple layers in the conventional GaAs MESFET, the change in the drain-source current of the device with respect to the gate voltage can be made step-like. It is possible to obtain a device suitable for use in a multivalued logic circuit.

[Brief explanation of the drawing]

FIG. 1 shows a GaA for multivalued logic circuit according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a laminated conductive region formed on the main surface of a GaAs substrate in an example of the GaAs device manufacturing method of the present invention, and FIG. 3 is a cross-sectional view showing a GaAs substrate. 4 is a cross-sectional view showing a state in which a channel region is formed on the main surface of a GaAs substrate. 6 is a graph showing the theoretical current-voltage characteristics of the GaAs device of the present invention. 1: Semi-insulating GaAs substrate, 2: Channel region, 3: ...Source region, 4...Drain region, 5...
- Gate electrode, 6... Ohmic electric bridge, 7... Passivation film, 8... Semi-insulating GaAs layer (semi-insulating layer), 9... N-type GaAs layer (conductive layer), 10...・
Laminated conductive region, 11...source electrode, 12...drain electrode, 13...depletion layer, 14...n shadow region, 1
5・Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5/θ Fig. 6 Kui S(v)

Claims (1)

[Scope of Claims] 1. A semiconductor device constituted by a Schottky gate field effect transistor, comprising a laminated conductive region in which a plurality of conductive layers are laminated between the gate and drain of the Schottky gate field effect transistor. A semiconductor device characterized by having: 2. The laminated conductive region is provided in a semi-insulating GaAs substrate, and includes an n-type GaAs layer and an undoped semi-insulating GaAs layer.
2. The semiconductor device according to claim 1, wherein the semiconductor device has a structure in which S layers are stacked alternately.