JPH012436A - clock extraction circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a clock extraction circuit for extracting clock pulses from received data in a signal receiving circuit of an optical transmission device in the field of optical communication, and particularly to a clock extraction circuit for extracting clock pulses from received data. This article is about the one-step phase adjustment method.

(Prior art) An extraction circuit that can extract a pulse repetition frequency component from a transmitted pulse train is used, for example, to identify the correct identification number in an identification circuit.
! , through the timing pulse necessary to change one point.
It is an L circuit. This clock extraction circuit has a
The output of the phase adjustment means and the timing extraction filter connected to the subsequent stage It is necessary to provide a pulse width adjustment means for adjusting the duty pressure.

In conventional clock extraction circuits, a method using a delay amount manipulation using the delay per unit length of a coaxial cable or a method using a delay line has been used as a clock phase adjustment means. Also, as a pulse width adjustment means, goo[
・Methods using differential circuits that utilize the delay of ・ and the delay of coaxial cables were used.

(Problems to be solved by the invention) However, the clock extraction circuit with the above configuration requires a coaxial cable for clock phase adjustment, a delay line, etc., which takes up a large space, and therefore has problems in terms of reliability and miniaturization. There was a problem. Further, the clock pulse width adjusting means also has problems such as a narrow variable width, lack of versatility, and time-consuming adjustment.

The present invention provides a clock extraction circuit that solves the problems of the prior art, such as low reliability, large size, narrow variable range, non-universality, and complicated adjustment. .

(Means for Solving the Problem) In order to solve the problem, the present invention provides a clock extraction circuit that extracts a clock pulse from an input signal, in which the input signal is differentiated and a first trigger pulse is output. a first differentiation circuit; a first monostable multivibrator with a variable pulse width triggered by the first trigger pulse; and a second trigger pulse obtained by differentiating the output signal of the first monostable multivibrator. a second differentiating circuit that outputs the second !; - A circuit that has a second monostable multivibrator with a variable pulse width triggered by a trigger pulse and outputs a regenerated clock pulse of a predetermined frequency.

(Function) According to the present invention, the above clock extraction circuit)
I completed 14, so here is the 1st one. By adjusting the second monostable multivibrator, it becomes possible to easily and accurately change the phase and pulse width of the clock pulse independently over a wide range. This enables integration together with the second differentiator circuit. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a conjunctive block diagram of a clock extraction circuit according to an embodiment of the present invention.

This clock extraction circuit is a circuit that is integrated in one chip in an optical signal receiving circuit, and has an input terminal 1 that inputs a pulsed input signal Sin, and outputs a pulsed output signal sout. Output terminal 2 and the person,
A first differentiating circuit 10, a first monostable multivibrator (monostable multivibrator) 20, a second differentiating circuit 30. The second monostable multivibrator 7IO1 and the positive/negative phase selection circuit 50 are sequentially connected in cascade.

1st. Behind the second differentiating circuit 10.30, the first differentiating circuit 10 is configured with an inverter or the like and has delay groups 1 to 11 which delay the input signal Sin from the pack terminal 1 by a predetermined time and output a delayed signal S11. , AND GO! takes the AND of the delayed signal 311 and the inverted signal of the input signal Sin and outputs the first trigger pulse 312! - (Hereinafter, AND
It consists of 12 gates (referred to as gates). Similarly, the second
The differentiating circuit 30 receives the output signal S2 of the first differentiating circuit 20.
0 is delayed for a predetermined time and the delayed signal 331 is sent to the delay gate 3.
1 and an AND gate 32 which performs a logical product of the delayed signal S31 and an inverted signal of the output signal S20 and outputs a second 1-ligation pulse S32.

Also number 1. Second monostable multivibrator 20°40
Among them, the first monostable multivibrator 20 has an externally attached variable resistor 60 to which the power supply voltage Vee is applied, and the first monostable multivibrator 20 has an external variable resistor 60 to which the power supply voltage Vee is applied.・This is a circuit that is triggered and outputs a pulse-like output signal +"3S20. Similarly, the second (7) q1 stable multivibrator 4
0 is a circuit that connects an external variable resistor 70 to which a power supply 7 or LEveO is applied, and outputs a pulsed output signal 340 by being triggered by the second trigger pulse S32. These first. The pulse widths of the output signals 320 and S/10 of the second instep stable multivibrator 20.40 are varied by variable resistors 60.70, respectively.

The positive/negative phase selection circuit connected to the output side of the second monostable multivibrator 40; or inversion, and apply the selection result to the clock pulse Sou.
This circuit sends the signal to the output terminal 2 in the form of t.

Figure 2 shows the monostable multivibrator 20 in Figure 1.
．． FIG. 3 is a circuit diagram of 40 (not shown) and a waveform diagram for explaining its operation.

This monostable multivibrator 20.40 has an input weak element 1 which inputs the trigger pulses S12 and S32 in the previous stage.
00, an output terminal 101 for outputting output signals S20 and S40, and a terminal 102 to which external variable resistors 60 and 70 are connected. Power supply voltage Vcc and tick rating 10
An integrated compound 1110 stabilized by an oxide film capacitor or the like and a constant current source 111 that outputs a constant current 1o are connected in series between the integrated capacitor 110 and the constant current source 1.
A charging/discharging transistor 112 and a (-) sub-input terminal of a voltage comparator 113 are connected to a connection point N of the voltage comparator 11 .

The (+) sub-input terminal of the voltage comparator 113 is connected to a constant current source 114 that outputs a constant current 1c, and is connected to a resistor 11.
5 to the output terminal of the voltage comparator 113. The output terminal of the voltage comparator 113 is a set/reset type flip-flop (hereinafter referred to as R3/"F") 116.
The set terminal S of R3/FF116 is connected to the input terminal 100, the output terminal Q is connected to the output terminal 101, and the inverted output terminal is connected to the transistor 1.
Each is connected to 12 bases.

In this monostable multivibrator 20.40, as shown in FIG. When the discharge voltage of the converter capacitor 116, that is, the converter Vin on the connection point N, is supplied to the (-) sub-input terminal of the voltage comparator 113, the magnitude of each voltage V[[1 and Vin is The voltage comparator 113
are compared. The voltage comparator 113 outputs a reset signal according to the comparison value between the two input terminals vth and Vin, and resets the R3-FF 116 through the reset terminal R. R
3.FF11G is set by the trigger pulse S12, 332 supplied to the Z terminal S, outputs output signals 1320, 340 with a pulse width Δ'' from the output terminal Q, and sends the inverted signal to the J4 seat switch (for inversion). 1 to transistor 112 are turned off. When transistor 112 is turned off, the integrated '3Ti! 110
is being charged. Here, if the capacitance value of the integrated quantity 110 is C, the pulse import t of the output signal 320 and S40 is ΔL = −(l Vin −Vth l
)O. Therefore, by changing the variable resistor 60.70 of the external Cpu, the constant current 1o changes, thereby making it possible to adjust the pulse width Δ°C.

The operation of the clock extraction circuit configured as described above is explained in the fourth section.
This will be explained with reference to the figures. FIG. 4 is a waveform diagram for explaining the operation of FIG. 1.

When a pulsed input signal Sin is supplied to the input terminal 1, the input signal Sin becomes a delayed signal S11 whose time is delayed by the delay gate 11 in the first differentiating circuit 10.
The input signal Sin and the delayed signal Sll are differentiated by the AND gate 12 at the rising edge of the input signal gsin, and the first monostable multivibrator 20 is set by the first trigger pulse 312 that is the result of the differentiation. Then the first
From the monostable multivibrator 20, the pulse width Δt1
An output signal S20 is output. The output signal 320 becomes a delayed signal gS31 whose time has been increased by iY by the delay gate 31 of the second differentiating circuit 3Q11, and the output signal 320
The delayed signal @S31 is differentiated at the falling edge of the output signal f'3s20, and the second monostable multivibrator 40 is activated by the second trigger pulse S32, which is the result of the differentiation. Or Sera 1 ~ will be done. When the second medium-stable multivibrator 4 ( ) is set, the second monostable multivibrator 40 outputs an output signal QS40 with a pulse width Δt2, and the output signal S40 is passed through the positive-phase and negative-phase selection circuit 50. The clock pulse 5out, which has the same phase or is inverted, is sent out from the output terminal 2.

Here, the output signal 320 of the first monostable multivibrator 20 is transmitted through an external variable resistor 60 and an integrated capacitor 110.
Since the phase of the second trigger pulse S32 outputted from the second differentiator circuit 30 can be freely adjusted by changing the external variable resistor 60. Furthermore, since the output signal 340 of the second single constant multi-vibrator 40 is determined by the time constant of the external variable resistor 70 and the integrated capacitor 110, changing the variable resistor 70 is not necessary. Its output signal 340 by
The pulse width Δt2 can be freely adjusted independently of the output signal S20. Moreover, the phase variable width of the reproduced clock pulse sout of the frequency fo is compensated by 180 degrees by the final stage positive phase and negative phase selection circuit 50.

The clock pulse Sout outputted from the positive phase and negative phase selection circuit 50 drives the next stage timing extraction filter connected to the output terminal 2.

This embodiment has the following advantages.

It is possible to integrate a clock extraction circuit, which conventionally required a large space, on a single chip, and it is possible to provide a space-saving lock extraction circuit that is highly reliable, especially in E-joule applications such as optical signal receiving circuits. In addition, since lock pulse adjustment and phase adjustment can be performed independently for the input signal Sin over a wide frequency range, it is possible to use it for general purposes, reduce the cost of integrated circuits, and make adjustments easy. This improves work efficiency.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of variations include the following.

(i) 1st. The second differentiating circuit 10.30 may be composed of other circuits. For example, in the first differentiating circuit 10, if only the aluminum pattern mask is changed and the AND gate 128 is replaced with an exclusive OR gate (XOR gate), the clock pulse sout of frequency 2fo becomes jJ
It will be done.

(ii) 1st. Second medium stable multivibrator 2
0 and 40 may be configured with other circuits.

(Effects of the Invention) As described in detail above, according to the present invention, at least the first. Since it is configured with a second differentiating circuit and a first and second monostable multivibrator, the phase of the clock pulse can be adjusted over a wide range with the first monostable multivibrator, and the clock pulse can be adjusted with the second monostable multivibrator. The pulse width can be adjusted over a wide frequency range independently of the pulse phase. In general, integration allows for miniaturization and high reliability of 1υ1, and
It is also possible to expect effects such as wide range adjustment of pulse width, general-purpose output, and simplification of adjustment.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a clock extraction circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram of the monostable multivibrator shown in FIG. 1, FIG. 3 is a waveform diagram of FIG. 2, and FIG. FIG. 2 is a waveform diagram of FIG. 1; 10, 30... 1st. second differentiation circuit, 20.
40... 1st. Second monostable multivibrator, 50... Positive phase and negative phase selection circuit, 60.70.
...Variable resistance.

Claims (1)

[Claims] 1. In a clock extraction circuit that extracts a clock pulse from an input signal, a first differentiation circuit that differentiates the input signal and outputs a first trigger pulse; a first monostable multivibrator whose pulse width is variable to be triggered; a second differentiator circuit which differentiates the output signal of the first monostable multivibrator and outputs a second trigger pulse; 1. A clock extraction circuit comprising: a second monostable multivibrator with a variable pulse width triggered by a trigger pulse; and an output circuit that outputs a regenerated clock pulse of a predetermined frequency. 2. The clock extraction circuit according to claim 1, wherein the output circuit is comprised only of the second monostable multivibrator. 3. The output circuit is connected to the second monostable multivibrator and the output side of the second monostable multivibrator, and selects and outputs either its output pulse or an inverted pulse of the output pulse. 2. A clock extraction circuit according to claim 1, comprising a positive phase/negative phase selection circuit. 4. The first differentiating circuit comprises a delay gate that delays the input signal, and an AND gate that takes an AND of an inverted signal of the input signal and an output of the delay gate. The clock extraction circuit described in item 1.