JPH01244526A - data transfer device - Google Patents

Abstract

PURPOSE:To dynamically change the control of data transfer processing in accordance with termination of pipeline processing and to omit the control for the postprocessing of pipeline processing by providing not only a function to perform the transfer processing matched to a word in the data area of the transfer destination but also an address management part which detects the end point of the data area of the transfer destination. CONSTITUTION:This device consists of a data queue 1 where transfer source data is stored, a circuit for bit alignment between the transfer source data area and the transfer destination data area, a register 6 where transfer destination data matched to the word of the transfer destination data area is stored, and an output address management part 8 which manages the transfer destination address to detect the end point of the transfer destination area. When the bit alignment processing and the data transfer processing are performed in parallel, pipeline processing and its postprocessing are controlled systematically. Thus, the control of the whole of pipeline processing is simplified and pipeline processing is easily used.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data transfer device in a data processing system using a storage device whose access unit is a word of fixed length bits.

2. Prior Art Conventional data transfer devices include, for example, Japanese Patent Laid-Open No. 61
-15796.2 (data transfer device).

FIG. 3 shows a block diagram of this conventional data transfer device. Numeral 31 is a data queue for storing transfer source data. Numeral 32 is a pointer pointing to a valid starting address of the data queue 31. When output to the bus, it points to the next valid address. 33 is a buffer register that stores data output to the internal bus; 34 is the buffer register 3;
A temporary register 35 stores the contents of the above-mentioned - time register as a first input, data on the above-mentioned internal bus as a second input, and 35 is a 2-word concatenation of the first and second inputs. 36 is a data buffer register that stores the output of the barrel shifter; 37 is the output of the data buffer register and the data of the corresponding transfer destination; 36 is a data buffer register that stores the output of the barrel shifter; This shows an arithmetic unit that performs arbitrary calculations during this period.

In the conventional data transfer device configured as described above, data is read into the data queue 31 from the transfer source address of the storage device, and 2-word length data is transferred using the -hour register buffer 33 and temporary register buffer 34. It is configured on the barrel shifter 35 and outputs one word worth of data from an arbitrary bit position to the data buffer register 36. The arithmetic unit 37 performs arithmetic operations on the contents of the data buffer register 36 and the corresponding transfer destination data, and writes the output to the corresponding word of the storage device.

Problems to be Solved by the Invention In the above configuration, parallel processing, so-called pipeline processing, is possible by operating the data queue, barrel shifter, and arithmetic unit in parallel. However, in order to process all the data to be transferred, first there is pre-processing that prepares the data for the data cue, barrel shifter, and arithmetic unit, then pipeline processing that processes each piece of data in parallel, and finally, the unprocessed data. Post-processing is required to process and output the remaining data in the second pipeline. In particular, post-processing is performed after detecting the end of transferred data during pipeline processing, stopping the pipeline processing, and controlling the end by detecting the end, stopping pipeline processing, and post-processing. There was a problem in that the execution of processing became complicated.

In view of the above, it is an object of the present invention to provide a data transfer device that facilitates control of the pipeline processing of the data transfer device and performs data transfer simply and at high speed.

Means for Solving the Problems The present invention provides a data queue for storing source data, a hit position matching circuit between the source data area and the destination data area, and a transfer destination that matches the words of the destination data area. This data transfer device includes a register that stores data and an output address management section that manages the transfer destination address and detects the end point of the transfer destination area.

Effect of the Invention The present invention has the above-described configuration, and has the function of performing transfer processing consistent with the words of the transfer destination data area, as well as an address management section that detects the end point of the transfer destination data area, thereby making it possible to terminate pipeline processing. Control of data transfer processing can be dynamically changed accordingly, and control for post-processing of pipeline processing can be omitted.

Embodiment FIG. 1 is a block diagram of a data transfer device in an embodiment of the present invention. In Figure 1, 1 is a data queue that stores the data of the transfer source, 2 is a data queue pointer that points to the valid start address of data queue 1,
When the contents of are output, it points to the next valid address. However, when an end point detection signal is sent from the output address management unit 8, which will be described later, this pointer is not updated. A buffer register 3 stores the contents of the internal bus at a designated timing, and outputs the contents to the next temporary register 4 at a second timing. 4 is a temporary register that stores the contents of the above-mentioned time register buffer at a specified second timing; 5 is a temporary register which takes the output from the temporary register as the first input, and uses the contents on the internal bus as the second input. ,
A barrel shifter outputs one consecutive word of data from an arbitrary bit of the word that connects the first and second inputs, 6 is a data buffer register that stores the output of the barrel shifter, 7 is a transfer destination word An arithmetic unit 8 performs an arbitrary operation between the contents of the data buffer register and the contents of the data buffer register, and an arithmetic unit 8 holds the transfer destination address, calculates the next transfer destination address, detects the end point of the transfer area, and sends the detection signal to the This is an output address management unit that outputs to the data queue pointer 2.

The operation of the data transfer apparatus of this embodiment configured as described above will be explained below using FIG. 2 as an example. FIG. 2 is an explanatory diagram of the operation of this embodiment, showing the case where the transfer source data area indicated by diagonal lines in FIG. 2(a) is transferred to the destination data area indicated by diagonal lines in FIG. The processing, its pre-processing, and post-processing will be explained.

Pre-processing for pipeline processing is processing for preparing data necessary for pipeline processing. This is the process of storing the transfer source data. In the case of the examples shown in FIGS. 2(a) and 2(b), the transfer source data stored in data queue 1 is output to the internal bus, stored by barrel shifter 5, and after bit alignment, transferred to data buffer register 6. This is the process of outputting. At this time, if the end signal is not output from the output address management section 8, the data queue pointer 2 is updated to point to the position of the next valid data in the data queue 1. This state diagram is shown in FIG. 2(C). Pipeline processing is parallel processing in which specified processing is performed on prepared data and the next data is prepared at the same time. In this embodiment, the transfer destination held in the data buffer register 6 These are an external process of transferring source data (hereinafter referred to as transfer data) that matches the word, and a parallel process of storing the next transfer data in the data buffer register 6. As external processing, first, the contents of the data buffer register 6 are outputted as the first input of the arithmetic unit 7. At the same time, the contents of the destination word are transferred to the arithmetic unit 7 as a second input via the external data bus.

The arithmetic unit 7 performs any predetermined arithmetic operation on these two human forces, and outputs the result to the destination. At this time, the output address management section 8 determines the next transfer destination address after the transfer data is output to the transfer destination. When the next transfer destination address matches the end word of the transfer destination area, the output address management unit 8 outputs a transfer end signal to the data queue pointer 2. Furthermore, the following internal processing is performed. First, the data buffer register 6 outputs the contents of the barrel shifter 5 to the arithmetic unit 7, and then converts the contents of the barrel shifter 5 to 1 from the designated bit position.
Stores one word. Next, the data cue 1 outputs the data indicated by the data cue pointer 2 to the internal bus, and is stored in the barrel shifter 5 together with the contents of the - hour register 4. The contents of buffer register 3 are temporarily stored, and after the output of sister 4, -
is stored in time register 4, and then buffer register 3-
2, the same content as that output from data queue 1 to data buffer register 6 is stored through the internal bus. The results of the above operation are shown in FIG. 2(d). The pipeline processing is repeated as many times as necessary.

FIG. 2(e) is a state diagram for the next round of pipeline processing. Finally, post-processing is a so-called clean-up process that outputs the data remaining unprocessed on the pipeline to the end, but in this embodiment, the data is stored in the data buffer register 6 as in pipeline processing. External processing for transferring existing data and internal processing for storing new data in data buffer register 6 are performed. However, in this case, since the end point detection signal of the output address management section is output, data queue pointer 2 is not updated, and the same data is repeatedly output from data queue 1, meaningless to data buffer register 6. data is stored.

Therefore, the post-processing has the same effect as if only external processing had been executed. This state diagram is shown in FIG. 2(f).

As described above, in this embodiment, post-processing of pipeline processing can be treated as the same processing as mid-pipeline processing. This means that if the device is controlled by a microprogram, post-processing of the pipeline can be performed by preparing only instructions for pipeline processing, and the instruction system can be simplified and the capacity of the control storage device can be reduced.

Although this embodiment shows a structure in which each register is directly connected, this is only used to clarify the flow of data;
Even if the structure is such that each register is connected by a common bus as in the example of the data transfer device), if the structure is such that data transfer between each register is performed on the common bus without duplication, Controlling the order of data transfer simplifies control, similar to the above-described embodiment in which registers are directly connected.

As explained in ``2, Effects of the Invention'', in the present invention, when performing bit position agitation processing and data transfer processing in parallel, it was previously necessary to perform complex control such as pipeline processing and its pre-processing and post-processing. However, by uniformly controlling pipeline processing and subsequent processing, the overall control of pipeline processing can be simplified and pipeline processing can be easily used, and its practical effects are as follows: big.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transfer device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the same embodiment, and FIG. 3 is a block diagram of a conventional data transfer device. 1.31...Data cue, 2.32...Data cue pointer, 3.33...
Buffer/register, 4.34...-Hour register, 5.35...Barrel shifter, 6.36...Data buffer register, -same 7.37...Arithmetic unit, 8...Output address Management Department. Name of agent: Patent attorney Toshio Nakao and one other personFigure 2Figure 2

Claims (1)

[Claims] An internal bus with a width of one word consisting of multiple bits, a data queue that stores the data of the transfer source and sequentially outputs the data to the internal bus, and a data queue that stores the data output from the data queue and that is designated as a barrel shifter that stores the output of the register buffer and the data on the internal bus as two consecutive words of data and outputs one consecutive word of data from an arbitrary bit position; A data buffer that stores data on the barrel shifter, an arithmetic unit that performs a desired operation between one word of data on the corresponding transfer destination and the data on the data buffer, and holds the address of the corresponding transfer destination. What is claimed is: 1. A data transfer device, further comprising an output address management unit that obtains a next transfer destination address and detects an end point address, and transfers the output of the calculation.