JPH01245460A - Buffered seeking circuit for fdd - Google Patents

Abstract

PURPOSE:To control a flexible disk drive (FDD) without changing respective configurations of the FDD, a flexible disk controller (FDC), and a system by changing a step rate set at the FDC to the one suitable for the FDD and masking an index signal and a read data signal until a seeking operation in the FDD is completed. CONSTITUTION:The title circuit 2 is connected between an FDD1 and an FDC3. The FDC3 generates a control signal in the buffered seeking circuit 2 for the FDD based on a control command received from a system 4. The buffered seeking circuit 2 for the FDD changes a step signal 5 from the FDC3 to the step rate suitable for the FDD1, outputs the step rate, and masks a read data signal 6 from the FDD1 and an index signal 7 from the FDD1 until the seeking operation in the FDD1 is completed. Thus, the FDD1 can be controlled without changing the respective configurations of the FDD1, the FDC3, and the system 4 and without a seeking error, a seeking noise, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffered seek circuit that controls an FDD.

[Prior Art] FIG. 4 is a block diagram showing a configuration for controlling a conventional FDD. In the figure, l is FDD, 3 is FDC, 4 is F
This is a system that controls DC3.

Next, the operation of controlling the conventional FDD described above will be explained. System 4 uses FDC3 to control FDD I.
Issue a control command to.

FDC3 outputs a control signal to FDDI I based on the control command received from system 4.

When FDDI I performs a seek operation, FDDI
Since the positioning stepping motor (not shown) is under open-loop control, the system 4 issues a control command to perform a seek operation at a step rate that matches the FDDI.

FDD I is read/write (Read-Write)
When performing an operation, the system 4 issues a read/write command to the FDC 3. Then, )'DC3 finds the target sector by the time it detects the index pulse twice, and the FDDI performs read/write operations.

[Problems to be Solved by the Invention] Since the configuration for controlling the conventional FDD is as described above, the FD that matches the step rate issued by the system 4 is
If DI is not used, seek errors, seek noise, etc. will occur, and for this reason, there is the inconvenience of having to select and use the FDDI that matches the step rate issued by System 4. There was a problem.

This invention was made to solve the above problems, and provides an FDD that can control the FDD without changing the configurations of the FDD, FDC, or system, and without causing seek errors, seek noise, etc. Buff 7-
The purpose is to obtain a doseek circuit.

[Means for Solving the Problems] The buffered seek circuit for FDD according to the present invention has the following features:
Connected between DD and FDC, l? Change the step rate set for Dc to one that matches FDD, and use this F
The index signal and read data signal are masked until the seek operation is completed in the DD.

[Function] The FDD buffer 7-do seek circuit in this invention has the following features:
It is connected between FDD and FDC, which allows F
An FDD with a large step rate can be connected without changing the DC or system configuration (control program).

[Embodiment] FIG. 1 is a block diagram showing a configuration for controlling an FDD using an FDD buffer seek circuit according to an embodiment of the present invention. In the figure, 1 is an FDD, 2 is a buffer seek circuit for the FDD, and 3 is a system that generates a control signal for controlling FDD I. FDC14 is a system that controls F and DC3.

FIG. 2 is a block diagram showing the configuration of the FDD buffer seek circuit of FIG. 1, and FIG. 3 is a diagram showing the timing of signals of each part in the FDD buffer seek circuit of FIG. 2.

In the figure, 5 is the step signal from FDC3, 6 is F
Read data signal from DD I, 7 is an index signal from FDDI, 8 is a counter circuit that counts up by step signal 5 and counts down by step signal from step signal generation circuit 9, 9 is F
A step signal generation circuit 10 generates a step signal with a step rate suitable for DD I; 10 is a read data signal from FD I; 6. A mask control circuit masks the index signal 7 from the FDDI until the seek end, and 11 is a step signal mask circuit that masks the step signal generated by the step signal generation circuit 9 when the count of the counter circuit 8 reaches "0". . Also, 1
2 is a step signal to FDD 1, ]3 is a read data signal to FDC3, 14 is an index signal to FDC3, 15 is a direction signal from FDC3, 16
17 is a direction latch circuit that latches the direction signal based on the step signal 5 from the FDC 3.

Next, the FDD buffer 7 which is an embodiment of the present invention will be described.
- Regarding the operation of controlling an FDD using a doseek circuit,
This will be explained with reference to FIGS. 1 to 3. System 4 shown in FIG. 1 issues control commands to FDC 3 to control FDDI. The FDC 3 generates a control signal to the FDD buffer seek circuit 2 based on the control command received from the system 4. F
The DD buffered seek circuit 2 changes the step signal 5 from the FDC 3 to a step rate that matches the FDD I, outputs it, and outputs the step signal 5 from the FDC 3 until the seek operation is completed in the FDDI.
Read data signal 6 from FDD I and FD shown in the figure
Mask the index signal 7 from DI.

That is, in the FDD buffer seek circuit 2 shown in FIG. 2, the step signal 5 from the FDC 3 causes the counter circuit 8 to count up. Further, the step signal generation circuit 9 generates a step signal with a step rate matching FDDI.

This step signal causes the counter circuit 8 to count down, and the step signal is roughly input to the step signal mask circuit 11. This step signal mask circuit 11
depends on whether the count of the counter circuit 8 is "0" or not. If the count is "0", the step signal is masked and output as the step signal 12 to the FDD I, and the step signal generating circuit 9 Reset. Based on the step signal 12 to FDDI, the mask control circuit 10 outputs the read data signal 6. from FDDI. The index signal 7 from FDDI is masked and the masked read data signal FDC
A read data signal 13 is sent to FDC3, and an index signal 14 is sent to FDC3, which is a masked index signal. Further, the direction signal 15 from the FDC3 is F
It is latched by the direction latch circuit 17 based on the step signal 5 from the DC 3, and becomes the direction signal 16 to the FDDI.

As mentioned above, the step signal 5 from the FDC 3 is input to the FDD by the FDD buffer 7-do seek circuit 2 according to the present invention.
The timing of the step signal 12 to DD I is as shown in FIG. 3. Also, read data signal 6 from FDDI. FDDI
The index signal 7 from the mask control circuit 10 of the FDD buffer 7-do-seek circuit 2 according to the present invention
Therefore, the seek operation is masked until the seek operation is completed at FDD I (the signal timing shown in Figure 3 includes the seek settle time), and the read data signal to FDC3, which is the masked read data signal, is masked.・Data signal 13. FDC, which is a masked index signal
The timing of the index signal 14 to 3 is as shown in FIG. 3.

[Effects of the Invention] As described above, the FDD buffer seek circuit of the present invention is connected between the FDD and the FDC, changes the step rate set by the FDC to one suitable for the FDD, and Since the index signal is configured to mask the read data signal until the seek operation in the FDD is completed, FDD.

A buffered seek circuit for an FDD that can control the FDD without changing the configurations (control programs) of the FDC and the system and without causing seek errors, seek noise, etc. can be obtained, which has an excellent effect. It is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration for controlling an FDD using a buffered seek circuit for FDD which is an embodiment of the present invention, and FIG. 2 shows a configuration of the buffered seek circuit for FDD shown in FIG. 1. Block diagram, Figure 3 is the FD of Figure 2
FIG. 4 is a block diagram showing the configuration for controlling a conventional FDD. In the figure, 1...FDD, 2...Buffered seek circuit for FDI), 3...FDC14...System, 5...Step signal from FDC3, 6...F
Read from DD I, data signal, 7...F I)
Index signal from DI, 8... Counter circuit, 9... Step generation circuit, lO... Mask control circuit, 11... Step signal mask circuit, 1
2...Step signal to F D D 1, 13...
Read data signal to FDC3, 14...FDC3
15...Direction signal from FDC3, 16...Direction signal to FDD I, 17...Direction latch circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] Connected between a flexible disk drive (FDD) and a flexible disk controller (FDC),
A buffer for an FDD characterized by having a function of changing the step rate generated from the FDC to one suitable for the FDD and masking an index signal and a read data signal until a seek operation is completed in this FDD. seek circuit.