JPH01246831A - Multilayer electrode wiring method - Google Patents
Multilayer electrode wiring methodInfo
- Publication number
- JPH01246831A JPH01246831A JP7520288A JP7520288A JPH01246831A JP H01246831 A JPH01246831 A JP H01246831A JP 7520288 A JP7520288 A JP 7520288A JP 7520288 A JP7520288 A JP 7520288A JP H01246831 A JPH01246831 A JP H01246831A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode wiring
- wiring
- wiring method
- multilayer electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000001953 recrystallisation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は多層電極配線法に関し、とりわけ半導体装置に
おけるＡρ電極配線又はＣｕ電極配線の配線・処理方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer electrode wiring method, and more particularly to a method for wiring and processing Aρ electrode wiring or Cu electrode wiring in a semiconductor device.
〔従来の技術１
従来、半導体装置におけるＡβ電極配線又はＣｕ電極配
線は、第１の電極配線上に形成されたＳｔｏｗ膜等から
成る絶縁膜を介し、該絶縁膜に開けられたコンタクト穴
を通して、第２の電極配線としてＡＩ又はＣｕ１／ｌ極
配線がなされるのが通例であった。[Prior art 1] Conventionally, Aβ electrode wiring or Cu electrode wiring in a semiconductor device is connected through an insulating film made of a Stow film or the like formed on a first electrode wiring, and through a contact hole made in the insulating film. It was customary to use AI or Cu1/l electrode wiring as the second electrode wiring.
［発明が解決しようとする課題］
しかし、上記従来技術によるとコンタクト部でのＡｉ又
はＣｕ膿のつきまわりが悪（、配線の段切れを起こした
り、マイグレーションによる断線を起こす等の課題があ
った。[Problems to be Solved by the Invention] However, according to the above-mentioned prior art, there were problems such as poor distribution of Ai or Cu pus at the contact portion (causing breakage of wiring and disconnection due to migration). .
本発明は、かかる従来技術の課題を解決するために、コ
ンタクト穴部のＡｆｌやＣｕ配線の表面が平滑になり、
且つ、マイグレーションによる断線を抑止する、主とし
て半導体装置におけるＡｌ又はＣｕ配線の形成・処理法
を提供する事を目的とする。In order to solve the problems of the prior art, the present invention makes the surfaces of the Afl and Cu wiring in the contact hole portion smooth,
Another object of the present invention is to provide a method for forming and processing Al or Cu wiring mainly in a semiconductor device, which suppresses disconnection due to migration.
［課題を解決するための手段］
上記課題を解決するために、本発明は、多層電極配線法
に係り、絶縁膜を介し、該絶縁膜に開けられたコンタク
ト穴を通して下層電極配線と多層にＡｌ１又はＣｕ電極
電線する場合に関し、ＷＳｉ又はＷ膜とＡρ又はＣｕ膿
の２層構造にて形成すると共に、前記Ａｊ２又はＣｕ膜
をレーザー・アニールあるいはランプ・アニールにより
再結晶化する手段をとる事、及び、前記ＷＳｉ又はＷ膜
をＣＶＤ法で形成する手段をとる。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a multilayer electrode wiring method, in which Al1 is connected to the lower electrode wiring and the multilayer through an insulating film and a contact hole made in the insulating film. Or in the case of a Cu electrode wire, forming a two-layer structure of WSi or W film and Aρ or Cu pus, and taking means to recrystallize the Aj2 or Cu film by laser annealing or lamp annealing. Then, the WSi or W film is formed by a CVD method.
〔実 施 例１
第１図は本発明の一実施例を示す、配線形成、処理法を
工程順に示したものである。すなわち、（ａ）半導体基
板１の表面に・は下層配線層となる拡散配線層２と層間
絶縁膜となるＳｉＯ２膜３が形成され、該Ｓ ｉ Ｏ２
膜３の前記下層配線層である拡散配線層２の上にはコン
タクト穴が開けられた後、ＣＶＤ法ニヨリＣＶＤＷＳｉ
膜４を形成後、Ｐ Ｖ Ｄ （Ｐｈｙｓｉｃａｌ Ｖａ
ｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ ）法としてスパッタ法
等によりＰＶＤＡｆｉ膜５を形成したもので、該ＰＶＤ
ＡＩ膜５は多結晶体であると共に、コンタクト内でのつ
きまわりが悪く、凹状に形成されて成る。次で（ｂ）表
面からレーザー光あるいはランプ光による光アニール６
の処理をＡｌ２膿の表面から施すことにより、Ａｌ膜は
融解、再結晶化し、単結晶化あるいは巨大結晶化すると
共に、コンタクト穴部はＡβに埋め込まれて成り、表面
が平滑になることとなる。[Embodiment 1] FIG. 1 shows an example of the present invention, in which wiring formation and processing methods are shown in the order of steps. That is, (a) a diffusion wiring layer 2 serving as a lower wiring layer and a SiO2 film 3 serving as an interlayer insulating film are formed on the surface of a semiconductor substrate 1, and the SiO2
After a contact hole is formed on the diffusion wiring layer 2, which is the lower wiring layer of the film 3,
After forming the film 4, P V D (Physical Va
The PVDAfi film 5 is formed by a sputtering method etc. as a por deposition method.
The AI film 5 is polycrystalline, has poor distribution within the contact, and is formed in a concave shape. Next, (b) optical annealing from the surface using laser light or lamp light 6
By performing this treatment from the surface of Al2P, the Al film melts, recrystallizes, becomes a single crystal or becomes a giant crystal, and the contact hole is filled with Aβ, resulting in a smooth surface. .
第２図は本発明の他の実施例を示す配線形成・処理法で
あり、半導体基板１１の表面には拡散配線層１２及びＳ
ｉＯ□膜１３膜形３され、該５ｉｎ２膜１３の前記拡散
配線層１２上に開けられたコンタクト穴を通して、ＣＶ
ＤＷＳｉ膜１４が前記コンタクト穴を埋める様に形成さ
れ、更に、該ＣＶＤＷＳｉ膜上にはＡ４膜等が形成され
、該Ａｌ膜は、光アニール１５により結晶化Ａ４膜１６
として形成・処理されて成る。これら下地ＷＳｉやＷ膜
光アニール時の耐熱膜としての作用があると共に、Ａｌ
１やＣｕ膿の再結晶化の種となる作用もある。FIG. 2 shows a wiring forming/processing method showing another embodiment of the present invention, in which a diffusion wiring layer 12 and an S
The CV
A DWSi film 14 is formed to fill the contact hole, and an A4 film or the like is further formed on the CVDWSi film, and the Al film is crystallized by photoannealing 15 to form a crystallized A4 film 16.
It is formed and processed as In addition to acting as a heat-resistant film during photo-annealing of these underlying WSi and W films, the Al
It also acts as a seed for recrystallization of 1 and Cu pus.
［発明の効果］
本発明により、マイグレーションによる断線やコンタク
ト穴部■の段切れの無い半導体装置におけるＡｌ又はＣ
ｕ配線を形成する事ができる効果がある。[Effects of the Invention] According to the present invention, Al or C can be used in a semiconductor device without wire breakage due to migration or break in the contact hole part (■).
This has the effect of making it possible to form a u-wiring.
第１図（ａ）、（ｂ）及び第２図は本発明の実施例を示
す、配線形成・処理法を示す図である。
■、１１・・・半導体基板
２．１２・・・拡散配線層
３．１３・・・ＳｉＯ□膜
４．１４・・−ＣＶＤＷＳｉ膜
５・・・・・・ＰＶＤＡｆｉ膜
６．１５・・・光アニール
７．１６・・・結晶化Ａβ膜
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 最 上 務（他１名）第１図
第２図FIGS. 1(a) and 2(b) and 2 are diagrams illustrating a wiring forming/processing method according to an embodiment of the present invention. ■, 11...Semiconductor substrate 2.12...Diffused wiring layer 3.13...SiO□ film 4.14...-CVDWSi film 5...PVDAfi film 6.15...Light Annealing 7.16...Crystallized Aβ film or above Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Mogami (1 other person) Figure 1 Figure 2
Claims (2)
穴を通して下層電極配線と多層にＡｌ又はＣｕ電極配線
する場合、ＷＳｉ又はＷ膜とＡｉ又はＣｕ膿の２層構造
にて形成すると共に、前記Ａｌ又はＣｕ膜をレーザー・
アニールあるいはランプ・アニールにより再結晶化する
事を特徴とする多層電極配線法。(1) When connecting a multilayer Al or Cu electrode wiring with a lower layer electrode wiring through an insulating film and a contact hole made in the insulating film, a two-layer structure of WSi or W film and Ai or Cu pus is formed. , the Al or Cu film is laser-treated.
A multilayer electrode wiring method characterized by recrystallization by annealing or lamp annealing.
とする請求項１記載の多層電極配線法。(2) The multilayer electrode wiring method according to claim 1, characterized in that the WSi film or the WSi film is formed by a CVD method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7520288A JPH01246831A (en) | 1988-03-29 | 1988-03-29 | Multilayer electrode wiring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7520288A JPH01246831A (en) | 1988-03-29 | 1988-03-29 | Multilayer electrode wiring method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01246831A true JPH01246831A (en) | 1989-10-02 |
Family
ID=13569375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7520288A Pending JPH01246831A (en) | 1988-03-29 | 1988-03-29 | Multilayer electrode wiring method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01246831A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266521A (en) * | 1991-03-20 | 1993-11-30 | Samsung Electronics Co., Ltd. | Method for forming a planarized composite metal layer in a semiconductor device |
| US5534463A (en) * | 1992-01-23 | 1996-07-09 | Samsung Electronics Co., Ltd. | Method for forming a wiring layer |
-
1988
- 1988-03-29 JP JP7520288A patent/JPH01246831A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869902A (en) * | 1990-09-19 | 1999-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US5266521A (en) * | 1991-03-20 | 1993-11-30 | Samsung Electronics Co., Ltd. | Method for forming a planarized composite metal layer in a semiconductor device |
| US5534463A (en) * | 1992-01-23 | 1996-07-09 | Samsung Electronics Co., Ltd. | Method for forming a wiring layer |
| US5589713A (en) * | 1992-01-23 | 1996-12-31 | Samsung Electronics Co., Ltd. | Semiconductor device having an improved wiring layer |
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